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Low-power, parasitic-insensitive interface circuit for capacitive microsensors

Low-power, parasitic-insensitive interface circuit for capacitive microsensors

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Capacitive transduction is ubiquitously employed at macro- and especially micro-scales due to their simple structure and stability. This study proposes a topology for a low-power readout circuit for differential capacitive sensors. The circuit includes two switched-capacitor blocks that produce signals that are proportional to the difference and sum of the sense capacitors. Outputs of these two blocks are fed to an analogue divider to produce a pulse whose width is proportional to the ratio of the difference to sum of the sense capacitors. In addition to providing adjustable sensitivity and noise levels, this also reduces the sensitivity of the sensor to common-mode parasitics at the circuit input. The circuit topology was realised in a standard CMOS 0.35 µm technology with a total chip area of 330 µm × 600 µm. The performance of the fabricated circuit was evaluated by pairing it with a micromechanical variable capacitor. Experimental results demonstrated the capability of the circuit to resolve 160 aF of differential capacitance with a total power consumption of 720 µW while remaining insensitive to common-mode parasitic capacitances.

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