RT Journal Article
A1 Cédric Bourrasset
AD Institut Pascal, Universite Blaise Pascal, Clermont Ferrand, France
A1 Luca Maggiani
AD Institut Pascal, Universite Blaise Pascal, Clermont Ferrand, France
AD TeCIP Institute, Scuola Superiore Sant'Anna, Pisa, Italy
A1 Jocelyn Sérot
AD Institut Pascal, Universite Blaise Pascal, Clermont Ferrand, France
A1 François Berry
AD Institut Pascal, Universite Blaise Pascal, Clermont Ferrand, France

PB iet
T1 Dataflow object detection system for FPGA-based smart camera
JN IET Circuits, Devices & Systems
VO 10
IS 4
SP 280
OP 291
AB Embedded computer vision based smart systems raise challenging issues in many research fields, including real-time vision processing, communication protocols or distributed algorithms. The amount of data generated by cameras using high resolution image sensors requires powerful computing systems to be processed at digital video frame rates. Consequently, the design of efficient and flexible smart cameras, with on-board processing capabilities, has become a key issue for the expansion of smart vision systems relying on decentralised processing at the image sensor node level. In this context, field programmable gate arrays (FPGA)-based platforms, supporting massive data parallelism, offer large opportunities to match real-time processing constraints compared with platforms based on general purpose processors. In this study, the authors describe the implementation, on such a platform, of a configurable object detection application, reformulated according to the dataflow model of computation. The application relies on the computation of the histogram of oriented gradients and a linear SVM-based classification. It is described using the CAPH programming language, allowing efficient hardware descriptions to be generated automatically from high level dataflow specifications without prior knowledge of hardware description languages such as VHDL or Verilog. Results show that the performance of the generated code does not suffer from a significant overhead compared with handwritten HDL code.
K1 linear SVM-based classification
K1 on-board processing
K1 high level dataflow specifications
K1 communication protocols
K1 CAPH programming language
K1 generated code
K1 hardware descriptions
K1 real-time processing constraints
K1 embedded computer vision
K1 oriented gradients
K1 distributed algorithms
K1 digital video frame rates
K1 smart vision systems
K1 real-time vision processing
K1 dataflow object detection system
K1 field programmable gate arrays
K1 configurable object detection
K1 high resolution image sensors
K1 flexible smart cameras
K1 massive data parallelism
K1 FPGA-based smart camera
DO https://doi.org/10.1049/iet-cds.2015.0071
UL https://digital-library.theiet.org/;jsessionid=348rqmu76cro3.x-iet-live-01content/journals/10.1049/iet-cds.2015.0071
LA English
SN 1751-858X
YR 2016
OL EN