http://iet.metastore.ingenta.com
1887

Dataflow object detection system for FPGA-based smart camera

Dataflow object detection system for FPGA-based smart camera

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Embedded computer vision based smart systems raise challenging issues in many research fields, including real-time vision processing, communication protocols or distributed algorithms. The amount of data generated by cameras using high resolution image sensors requires powerful computing systems to be processed at digital video frame rates. Consequently, the design of efficient and flexible smart cameras, with on-board processing capabilities, has become a key issue for the expansion of smart vision systems relying on decentralised processing at the image sensor node level. In this context, field programmable gate arrays (FPGA)-based platforms, supporting massive data parallelism, offer large opportunities to match real-time processing constraints compared with platforms based on general purpose processors. In this study, the authors describe the implementation, on such a platform, of a configurable object detection application, reformulated according to the dataflow model of computation. The application relies on the computation of the histogram of oriented gradients and a linear SVM-based classification. It is described using the CAPH programming language, allowing efficient hardware descriptions to be generated automatically from high level dataflow specifications without prior knowledge of hardware description languages such as VHDL or Verilog. Results show that the performance of the generated code does not suffer from a significant overhead compared with handwritten HDL code.

References

    1. 1)
      • M. Graphics , H. Tool . (2010)
        1. Graphics, M., Tool, H.: ‘Catapult c’, 2010.
        .
    2. 2)
      • J. Frigo , M. Gokhale , D. Lavenier .
        2. Frigo, J., Gokhale, M., Lavenier, D.: ‘Evaluation of the streams-c c-to-fpga compiler: an applications perspective’. Proc. of the 2001 ACM/SIGDA Ninth Int. Symp. on Field Programmable Gate Arrays, 2001, pp. 134140.
        . Proc. of the 2001 ACM/SIGDA Ninth Int. Symp. on Field Programmable Gate Arrays , 134 - 140
    3. 3)
      • A. Antola , M. Santambrogio , M. Fracassi .
        3. Antola, A., Santambrogio, M., Fracassi, M., et al: ‘A novel hardware/software codesign methodology based on dynamic reconfiguration with impulse c and codeveloper’. 2007 third Southern Conf. on. IEEE Programmable Logic, 2007, SPL'07.2007, pp. 221224.
        . 2007 third Southern Conf. on. IEEE Programmable Logic, 2007, SPL'07. , 221 - 224
    4. 4)
      • Y. Yankova , K. Bertels , S. Vassiliadis .
        4. Yankova, Y., Bertels, K., Vassiliadis, S., et al: ‘Automated hdl generation: Comparative evaluation’. IEEE Int. Symp. on Circuits and Systems, 2007. ISCAS 2007,May 2007, pp. 27502753.
        . IEEE Int. Symp. on Circuits and Systems, 2007. ISCAS 2007, , 2750 - 2753
    5. 5)
      • J. Eker , J. Janneck . (2003)
        5. Eker, J., Janneck, J.: ‘Cal language report’. University of California at Berkeley California, Berkeley, CA 94720, USA, Technical Memorandum, 2003.
        .
    6. 6)
    7. 7)
      • J. Sérot , G. Quénot , B. Zavidovique .
        7. Sérot, J., Quénot, G., Zavidovique, B.: ‘Functional programming on a dataflow architecture: applications in real-time image processing’, Mach. Vis. Appl., 1993, 7, (1), pp. 4456. Available at http://dx.doi.org/10.1007/BF01212416.
        . Mach. Vis. Appl. , 1 , 44 - 56
    8. 8)
    9. 9)
      • J. Sérot , F. Berry , S. Ahmed . (2013)
        9. Sérot, J., Berry, F., Ahmed, S.: ‘Caph: a language for implementing stream-processing applications on fpgas’, in Athanas, P., Pnevmatikatos, D., Sklavos, N. (Eds.): ‘Embedded Systems Design with FPGAs’, (Springer, New York, 2013), pp. 201224. Available at http://dx.doi.org/10.1007/978-1-4614-1362-2_9.
        .
    10. 10)
      • J. Sérot , F. Berry , C. Bourrasset .
        10. Sérot, J., Berry, F., Bourrasset, C.: ‘High-level dataflow programming for real-time image processing on smart cameras’, J. Real-Time Image Process., 2014, pp. 113. Available at : http://dx.doi.org/10.1007/s11554-014-0462-6.
        . J. Real-Time Image Process. , 1 - 13
    11. 11)
      • 11. ‘The Caph Programming Language home page’. Available at http://caph.univ-bpclermont.fr.
        .
    12. 12)
      • N. Dalal , B. Triggs .
        12. Dalal, N., Triggs, B.: ‘Histograms of oriented gradients for human detection’, Schmid, C., Soatto, S., Tomasi, C.(Eds.) in ‘International Conference on Computer Vision & Pattern Recognition’, (Eds.): June 2005, vol. 2, pp. 886893. Available at http://lear.inrialpes.fr/pubs/2005/DT05.
        .
    13. 13)
      • V. Vapnik . (1982)
        13. Vapnik, V.: ‘Estimation of dependences based on empirical data: Springer series in statistics (Springer Series in Statistics)’ (Springer-Verlag New York, Inc., Secaucus, NJ, USA, 1982).
        .
    14. 14)
      • C. Cortes , V. Vapnik .
        14. Cortes, C., Vapnik, V.: ‘Support-vector networks’, Mach. Learn., 1995, 20, (3), pp. 273297,. Available at http://dx.doi.org/10.1007/BF00994018.
        . Mach. Learn. , 3 , 273 - 297
    15. 15)
    16. 16)
    17. 17)
      • S. Bauer , S. Kohler , K. Doll .
        17. Bauer, S., Kohler, S., Doll, K., et al: ‘Fpga-gpu architecture for kernel svm pedestrian detection’. 2010 IEEE Computer Society Conf. on Computer Vision and Pattern Recognition Workshops (CVPRW), June 2010, pp. 6168.
        . 2010 IEEE Computer Society Conf. on Computer Vision and Pattern Recognition Workshops (CVPRW) , 61 - 68
    18. 18)
      • M. Hahnle , F. Saxen , M. Hisung .
        18. Hahnle, M., Saxen, F., Hisung, M., et al: ‘Fpga-based real-time pedestrian detection on high-resolution images’. 2013 IEEE Conf. on Computer Vision and Pattern Recognition Workshops (CVPRW), June 2013, pp. 629635.
        . 2013 IEEE Conf. on Computer Vision and Pattern Recognition Workshops (CVPRW) , 629 - 635
    19. 19)
      • Q. Zhu , M.-C. Yeh , K.-T. Cheng .
        19. Zhu, Q., Yeh, M.-C., Cheng, K.-T., et al: ‘Fast human detection using a cascade of histograms of oriented gradients’. Proc. of the 2006 IEEE Computer Society Conf. on Computer Vision and Pattern Recognition – Volume 2, ser. CVPR ‘06.Washington, DC, USA: IEEE Computer Society, 2006, pp. 14911498. Available at http://dx.doi.org/10.1109/CVPR.2006.119.
        . Proc. of the 2006 IEEE Computer Society Conf. on Computer Vision and Pattern Recognition – Volume 2, ser. CVPR ‘06. , 1491 - 1498
    20. 20)
      • F. Porikli .
        20. Porikli, F.: ‘Integral histogram: a fast way to extract histograms in cartesian spaces’. Proc. IEEE Conf. on Computer Vision and Pattern Recognition, 2005, pp. 829836.
        . Proc. IEEE Conf. on Computer Vision and Pattern Recognition , 829 - 836
    21. 21)
    22. 22)
      • T. Joachims .
        22. Joachims, T.: ‘Svmlight: support vector machine’, 1999, 19, (4).
        . , 4
    23. 23)
    24. 24)
      • R. Kadota , H. Sugano , M. Hiromoto .
        24. Kadota, R., Sugano, H., Hiromoto, M., et al: ‘Hardware architecture for hog feature extraction’. Proc. of the 2009 Fifth Int. Conf. on Intelligent Information Hiding and Multimedia Signal Processing, ser. IIH-MSP ’09, Washington, DC, USA: IEEE Computer Society, 2009, pp. 13301333. Available at http://dx.doi.org/10.1109/IIH-MSP.2009.216.
        . Proc. of the 2009 Fifth Int. Conf. on Intelligent Information Hiding and Multimedia Signal Processing, ser. IIH-MSP ’09 , 1330 - 1333
    25. 25)
      • K. Mizuno , Y. Terachi , K. Takagi .
        25. Mizuno, K., Terachi, Y., Takagi, K., et al: ‘Architectural study of hog feature extraction processor for real-time object detection’. 2012 IEEE Workshop on Signal Processing Systems (SiPS), October 2012, pp. 197202.
        . 2012 IEEE Workshop on Signal Processing Systems (SiPS) , 197 - 202
    26. 26)
      • J. Sérot , F. Berry , S. Ahmed .
        26. Sérot, J., Berry, F., Ahmed, S.: ‘Implementing stream-processing applications on fpgas: a dsl-based approach’. 2011 Int. Conf. on Field Programmable Logic and Applications (FPL), 2011, pp. 130137.
        . 2011 Int. Conf. on Field Programmable Logic and Applications (FPL) , 130 - 137
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2015.0071
Loading

Related content

content/journals/10.1049/iet-cds.2015.0071
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address