access icon free CMOS injection-locked frequency divider with division factor of three

A divide-by-3 injection locked frequency divider is presented. The divider works based on a two-stage differential ring oscillator in which two quadrature signals are used as injection signals. The analytical relationship for the divider locking range is derived and the main factors impacting on this parameter are discussed. The circuit has been designed in a 0.18 μm CMOS technology with a supply voltage of 1.8 V. Post layout simulation on the divider including all layout wiring parasitic elements such as resistance, capacitance and inductance shows that the typical locking range of the divider is over 3 GHz from 1 to 4.2 GHz for −0.5 dBm injection signal level while its total power dissipation for 4.2 GHz input injection signal is 505 μW at the supply of 1.8 V.

Inspec keywords: frequency dividers; injection locked oscillators; wiring; inductance; electric resistance; capacitance; CMOS integrated circuits; integrated circuit layout

Other keywords: injection signal; resistance; quadrature signal; three division factor; size 0.18 mum; complementary metal oxide semiconductor; capacitance; layout wiring parasitic element; CMOS technology; divider locking range; frequency 1 GHz to 4.2 GHz; two-stage differential ring oscillator; voltage 1.8 V; divide-by-3 injection locked frequency divider; inductance; power 505 muW; power dissipation

Subjects: Convertors; Semiconductor integrated circuit design, layout, modelling and testing; CMOS integrated circuits; Oscillators

References

    1. 1)
    2. 2)
    3. 3)
      • 11. Dehghani, R.: ‘A wideband CMOS divide-by-3 injection-locked frequency divider’. 21st Iranian Conf. on Electrical Engineering (ICEE), 2013, pp. 14.
    4. 4)
      • 12. Ponnambalam, M., Chandramani, P.: ‘Injection locked differential ring VCO’. IEEE Conf. on Information and Communication Technologies (ICT), 2013, pp. 424427.
    5. 5)
    6. 6)
    7. 7)
    8. 8)
    9. 9)
    10. 10)
    11. 11)
      • 9. Hara, S., Okada, K., Matsuzawa, A.: ‘10 MHz to 7 GHz quadrature signal generation using a divide-by−4/3, −3/2, −5/3, −2, −5/2, −3, −4, and −5 injection-locked frequency divider’. IEEE Symp. on VLSI Circuits (VLSIC), 2010, pp. 5152.
    12. 12)
      • 25. Ke, P.-C., Chiang, Y.-C.: ‘A 3.26-to-4.38 GHz divide-by-3 injection-locked frequency divider’. Asia-Pacific Microwave Conf. Proc. (APMC), 2010, pp. 22832286.
    13. 13)
      • 23. ‘Phase Noise Characterization of Microwave Oscillators- Frequency Discriminator Method’, Hewlett Packard, Product Note 11729C-2, 1985.
    14. 14)
    15. 15)
    16. 16)
    17. 17)
    18. 18)
    19. 19)
    20. 20)
    21. 21)
    22. 22)
      • 24. Huang, C.-J., Liu, C.-C., Jang, S.-L.: ‘A 0.35 μm CMOS divide-by-3 LC injection-locked frequency divider’. Int. Symp. on VLSI Design, Automation and Test, 2009, pp. 303306.
    23. 23)
    24. 24)
      • 14. Dehghani, R.: ‘Design of CMOS operational amplifiers’ (Artech House, Boston, 2013).
    25. 25)
    26. 26)
    27. 27)
    28. 28)
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2014.0363
Loading

Related content

content/journals/10.1049/iet-cds.2014.0363
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading