H.264/AVC is regarded as a popular video coding standard, and is widely used in multimedia applications. However, with an increasing demand for better quality videos, high efficiency video coding (HEVC) is all set to serve as the successor to H.264/AVC for higher resolution video applications. Since a majority of the multimedia devices have already been operating based on the H.264/AVC standard, it may not be worthwhile to completely replace the existing software and hardware components by different modules in order to adopt HEVC in such devices. Need is therefore felt to design a decoder for supporting H.264/AVC as well as HEVC, rather than attempting individual designs. This paper introduces a new dual-standard deblocking filter architecture, which supports both H.264/AVC and HEVC standards. Algorithmic verification has been done in Matlab and then an appropriate VLSI architecture has been implemented on FPGA as well as in ASIC domain. The proposed architecture takes 26 clock cycles for H.264/AVC and 14 cycles for HEVC to complete the filtering of a 16 × 16 pixel block. It consumes 5.80 mW normalised power and occupies an area equivalent to 70.1k equivalent gate at frequency of 100 MHz. The proposed architecture takes 8.42 ms to filter the 4K ultra high definition (UHD) (3840 × 2160) frame in H.264 standard, and it takes 18 ms to filter the 8K UHD (7680 × 4320) frame in HEVC standard.

References

1. 1)
  - 18. http://www.ses.com/4233325/news/2014/19709182.
2. 2)
  - 11. Ozcan, E., Adibelli, Y., Hamzaoglu, I.: ‘A high performance deblocking filter hardware for high efficiency video coding’, IEEE Trans. Consum. Electron., 2013, 59, (3), pp. 714–720 (doi: 10.1109/TCE.2013.6626260).
3. 3)
  - 21. Chien, C., Jian, G., Chang, H., et al: ‘High efficiency data access system architecture for deblocking filter supporting multiple video coding standards’, IEEE Trans. on Consum. Electron., 2012, 58, (2), pp. 670–678 (doi: 10.1109/TCE.2012.6227475).
4. 4)
  - 22. Chuang, T.-D., Tsung, P.-K., Lin, P.-C., et al: ‘A 59.5 mW scalable/multi-view video decoder chip for quad/3D full HDTV and video streaming applications’. Proc. IEEE Int. Solid-State Circuits Conf. (ISSCC-2010), 7 − 11 February 2010, San Francisco, pp. 330–331, DOI: 10.1109/ISSCC.2010.5433908.
5. 5)
  - 10. Lin, Y.C., Lin, Y.L.: ‘A two-result-per-cycle de-blocking filter architecture for QFHDH.264/AVC decoder’, IEEE Trans. Very Large Scale Integr.(VLSI) Syst., 2009, 17, (6), pp. 838–843 (doi: 10.1109/TVLSI.2008.2008456).
6. 6)
  - 8. Ugur, K., Andersson, K., Fuldseth, A.: ‘High performance, low complexity video coding and the emerging HEVC standard’, IEEE Trans. Circuits Syst. Video Technol., 2010, 20, (12), pp. 1688–1697 (doi: 10.1109/TCSVT.2010.2092613).
7. 7)
  - 19. http://www.eutelsat.com/en/news/press-releases/2014/Eutelsat-launches-ultra-hd-demo-channel-HEVC.html.
8. 8)
  - 13. Chen, Z.-D., Wan-Ming, L., Liang-Hao, W., Ming, Z., Wel, Z.: ‘A performance optimized architecture of deblocking filter for H.264’, J. China Univ. Posts Telecommun., 2007, 14, pp. 84–88 (doi: 10.1016/S1005-8885(08)60018-7).
9. 9)
  - 5. Kossentini, F., Mahdi, N., Guermazi, H.: ‘Informal subjective quality comparison of compression performance of HEVC working draft 5 with AVC high profile’. JCTVCH0562 JCTVC Eighth Meeting, San José, CA, February 2012.
10. 10)
  - 15. Zhu, J., Zhou, D., Satoshi, G.: ‘A high performance HEVC deblocking filter and SAO architecture for UHDTV decoder’, IEICE Trans. Fundam. Spec. Sect. Very Large Scale Integr (VLSI) Des. CAD Algorithms, 2013, E96-A, (12), pp. 2612–2622.
11. 11)
  - 2. Sullivan, G.J., Ohm, J.-R., Han, W.-J., Wiegand, T.: ‘Overview of the high efficiency video coding (HEVC) standard’, IEEE Trans. Circuits Syst. Video Technol., 2012, 22, (12), pp. 1649–1668 (doi: 10.1109/TCSVT.2012.2221191).
12. 12)
  - 17. Li, M., Zhou, J., Zhou, D., Xiao, P., Satoshi, G.: ‘Deblocking filter design for HEVC and H.264/AVC’. Proc. 13th Pacific-Rim Conf. on Advances in Multimedia Information Processing (PCM 2012), December 2012, vol. 7674, pp. 273–284.
13. 13)
  - 6. Richardson, I.: ‘An introduction to high efficiency video coding’ (V Codex Ltd. White Paper, 2013), http://www.vcodex.com.
14. 14)
  - 3. Bross, B., Han, W.J., Sullivan, G.J., Ohm, J.R., Wiegand, T.: ‘High efficiency video coding (HEVC) text specification draft 9’. Document JCTVC-K1003, ITU-T/ISO/IEC Joint Collaborative Team on Video Coding (JCT-VC), October 2012.
15. 15)
  - 14. Norkin, A., Bjøntegaard, G., Fuldseth, A., et al: ‘HEVC deblocking filter’, IEEE Trans. Circuits Syst. Video Technol., 2012, 22, (12), pp. 1746–1754 (doi: 10.1109/TCSVT.2012.2223053).
16. 16)
  - 7. List, P., Joch, A., Lainema, J., Bjøntegaard, G., Karczewicz, M.: ‘Adaptive deblocking filter’, IEEE Trans. Circuits Syst. Video Technol., 2003, 13, (7), pp. 614–619 (doi: 10.1109/TCSVT.2003.815175).
17. 17)
  - 12. Zhou, D., Zhou, J., Zhu, J., Goto, S.: ‘A 48 cycles/MB H.264/AVC deblocking filter architecture for ultra high definition applications’, IEICE Trans. Fundam., 2009, E92-A, (12), pp. 3203–3210 (doi: 10.1587/transfun.E92.A.3203).
18. 18)
  - 4. Li, B., Sullivan, G.J., Xu, J.: ‘Comparison of compression performance of HEVC working draft 5 with AVC high profile’. JCTVC-H0360, JCTVC Eighth Meeting, San José, CA, February 2012.
19. 19)
  - 2. Joint Collaborative Team on Video Coding (JCT-VC) of ITU-TSG 16WP 3 and ISO/IECJTC1/SC29/WG 11: ‘High efficiency video coding (HEVC) text specification draft 10 (for FDIS & Last Call)’, January 2013.
20. 20)
  - 9. Xu, K., Choy, C.S.: ‘A five-stage pipeline, 204 cycles/MB, single-port SRAM-based deblocking filter for H.264/AVC’, IEEE Trans. Circuits Syst., 2008, 18, (3), pp. 363–374.
21. 21)
  - 16. Shen, W., Shang, Q., Shen, S., et al: ‘A high-throughput VLSI architecture for Deblocking filter in HEVC’. IEEE Int. Symp. on Circuits and Systems (ISCAS), 2013, pp. 673–676, 19–23 May 2013, DOI: 10.1109/ISCAS.2013.6571936.
22. 22)
  - 1. Joint Video Team of ITU-T and ISO/IEC JTC 1: ‘Draft ITU-T recommendation and final draft international standard of joint video specification (ITU-T Rec. H.264 | ISO/IEC 14496-10 AVC’, January 2012.

High-speed low-power very-large-scale integration architecture for dual-standard deblocking filter

References

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