Design of a 56 Gbit/s 4-level pulse-amplitude-modulation inductor-less vertical-cavity surface-emitting laser driver integrated circuit in 130 nm BiCMOS technology

Guido Belfiore; Laszlo Szilagyi; Ronny Henker; Udo Jörges; Frank Ellinger

Design of a 56 Gbit/s 4-level pulse-amplitude-modulation inductor-less vertical-cavity surface-emitting laser driver integrated circuit in 130 nm BiCMOS technology

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Author(s): Guido Belfiore ¹ ; Laszlo Szilagyi ¹ ; Ronny Henker ¹ ; Udo Jörges ¹ ; Frank Ellinger ¹
- Affiliations: 1: Chair for Circuit Design and Network Theory, Dresden University of Thechnology, Helmholtzstrasse 18, 01069 Dresden, Germany
Source: Volume 9, Issue 3, May 2015, p. 213 – 220
DOI: 10.1049/iet-cds.2014.0240 , Print ISSN 1751-858X, Online ISSN 1751-8598

Received 24/03/2014, Accepted 16/09/2014, Published 01/05/2015

This paper presents the design and analysis of a 4-level pulse-amplitude-modulation (4-PAM) 56 Gbit/s vertical-cavity surface-emitting laser (VCSEL) driver integrated circuit (IC) for short range, high speed and low power optical interconnections. An amplitude modulated signal is necessary to overcome the bottleneck of speed given by the actual VCSELs and decrease the power consumption per bit. A prototype IC is developed in a standard 130 nm BiCMOS technology. The circuit converts two single-ended input signals to a 4-level signal fed to the laser. The driver also provides the DC current and the voltage necessary to bias the VCSEL. The power dissipation of the driver is only 115 mW including both the VCSEL and the 50 Ω input single-to-differential-ended converters. To the author's knowledge this is the first 56 Gbit/s 4-PAM laser driver implemented in silicon with a power dissipation per data-rate (DR) of 2.05 mW/Gbit/s including the VCSEL making it the most power efficient, 56 Gbit/s, common cathode laser driver. The active area occupies 0.056 mm². The small signal bandwidths are 49 GHz for the high and 43 GHz for the low amplitude amplification path, when the VCSEL is not connected. The bit error rate was tested electrically showing and error free connection at 28 GBaud/s.

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Design of a 56 Gbit/s 4-level pulse-amplitude-modulation inductor-less vertical-cavity surface-emitting laser driver integrated circuit in 130 nm BiCMOS technology

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