© The Institution of Engineering and Technology
This paper reports an analytical approach to predict the reference spur of a conventional frequency synthesiser more accurately in comparison with the existing technique where the ripple voltage waveform at voltage controlled oscillator input is approximated by narrow rectangular pulse. In this work, the ripple voltage waveform is represented by a combination of triangular and rectangular pulses. Transistor level SPICE simulations show that using the proposed approach, the error in the predicted spur has been reduced from about 29.84 to 0.64 dB. Measured result shows 4.39 dB error in the predicted spur. The derived expression has been extended further to predict the spur in frequency synthesisers having pulse repetition-based spur reducing technique including the repetition mismatch.
References
-
-
1)
-
7. Mandal, D., Mandal, P., Bhattacharyya, T.K.: ‘Spur suppression in frequency synthesizer using switched capacitor array’. Int. System-on-Chip (SoC) Design Conf., November 2012, pp. 100–103.
-
2)
-
19. ZigBee Specifications: .
-
3)
-
10. Razavi, B.: ‘Challenges in the design of frequency synthesizers for wireless applications’. Proc. IEEE Custom Integrated Circuits Conf., May 1997, pp. 395–402.
-
4)
-
12. Lee, T.-C., Lee, W.-L.: ‘A spur suppression technique for phase-locked frequency synthesizers’. IEEE Int. Solid-State Circuits Conf., February 2006, pp. 2432–2441.
-
5)
-
15. Kamal, N., Al-Sarawi, S., Abbott, D.: ‘An accurate analytical spur model for an integer-N phase-locked loop’. Int. Conf. on Intelligent and Advanced Systems, June 2012, vol. 2, pp. 659–664.
-
6)
-
20. Chen, J.-S., Ker, M.-D.: ‘Impact of gate tunneling leakage on performances of phase locked loop circuit in nanoscale CMOS technology’. Proc. IEEE Int. Reliability Physics Symp., April 2007, pp. 664–665.
-
7)
-
10. Yun, S.-J., Lee, H.D., Kim, K.-D., Kwon, J.-K.: ‘Differentially-tuned low-spur PLL using 65 nm CMOS process’, Electron. Lett., 2011, 47, (6), pp. 369–371 (doi: 10.1049/el.2011.0166).
-
8)
-
18. Razavi, B.: ‘RF microelectronics’ (Prentice-Hall, Inc., 1998).
-
9)
-
6. Hwang, I.-C., Bae, S.-G.: ‘Low-glitch, high-speed charge-pump circuit for spur minimisation’, Electron. Lett., 2009, 45, (25), pp. 1273–1274 (doi: 10.1049/el.2009.2660).
-
10)
-
12. Elsayed, M.M., Abdul-Latif, M., Sanchez-Sinencio, E.: ‘A spur-frequency-boosting PLL with a −74 dBc reference-spur suppression in 90 nm digital CMOS’, IEEE J. Solid-State Circuits, 2013, 48, (9), pp. 2104–2117 (doi: 10.1109/JSSC.2013.2266865).
-
11)
-
21. Hung, C.-C., Liu, S.-I.: ‘A leakage-compensated PLL in 65-nm CMOS technology’, IEEE Trans Circuits and Syst. II, Express Briefs, 2009, 56, (7), pp. 525–529 (doi: 10.1109/TCSII.2009.2020948).
-
12)
-
6. Charles, C.T., Allstot, D.J.: ‘A calibrated phase/frequency detector for reference spur reduction in charge-pump PLLs’, IEEE Trans. Circuits Syst. II, Express Briefs, 2006, 53, (9), pp. 822–826 (doi: 10.1109/TCSII.2006.880030).
-
13)
-
17. Lee, T.-C., Razavi, B.: ‘A stabilization technique for phase-locked frequency synthesizers’, IEEE J. Solid-State Circuits, 2003, 38, (6), pp. 888–894 (doi: 10.1109/JSSC.2003.811879).
-
14)
-
11. Liang, C.-F., Chen, H.-H., Liu, S.-I.: ‘Spur-suppression techniques for frequency synthesizers’, IEEE Trans. Circuits Syst. II, Express Briefs, 2007, 54, (8), pp. 653–657 (doi: 10.1109/TCSII.2007.896938).
-
15)
-
11. Vaucher, C., Kasperkovitz, D.: ‘A wide-band tuning system for fully integrated satellite receivers’, IEEE J. Solid-State Circuits, 1998, 33, (7), pp. 987–997 (doi: 10.1109/4.701238).
-
16)
-
2. Gardner, F.M.: ‘Phaselock techniques’ (John Wiley & Sons, Inc., 3rd edn.).
-
17)
-
8. Curticapean, F., Niittylahti, J.: ‘Exact analysis of spurious signals in direct digital frequency synthesisers due to phase truncation’, Electron. Lett., 2003, 39, (6), pp. 499–501 (doi: 10.1049/el:20030366).
-
18)
-
14. Thambidurai, C., Krishnapura, N.: ‘On pulse position modulation and its application to PLLs for spur reduction’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2011, 58, (7), pp. 1483–1496 (doi: 10.1109/TCSI.2011.2157749).
-
19)
-
14. Zhang, B., Allen, P.E., Huard, J.M.: ‘A fast switching PLL frequency synthesizer with an on-chip passive discrete-time loop filter in 0.25-μm CMOS’, IEEE J. Solid-State Circuits, 2003, 38, (6), pp. 855–865 (doi: 10.1109/JSSC.2003.811874).
-
20)
-
13. Choi, J., Kim, W., Lim, K.: ‘A spur suppression technique using an edge-interpolator for a charge-pump PLL’, IEEE Trans. Very Large Scale Integr. Syst., 2012, 20, (5), pp. 969–973 (doi: 10.1109/TVLSI.2011.2129602).
-
21)
-
4. Cho, S.H., Lee, H.D., Kim, K.-D., Ryu, S.T., Kwon, J.-K.: ‘Dual-mode VCO gain topology for reducing in-band noise and reference spur of PLL in 65 nm CMOS’, Electron. Lett., 2010, 46, (5), pp. 335–337 (doi: 10.1049/el.2010.3553).
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