Recent high-speed digital-to-analogue converters (DACs) cannot be easily characterised at their highest rate because of the very high cost of commercially available bit-error rate testers at the required DACs rate. Among possible solutions, an inexpensive approach is the use of a multiplexer (MUX) with built-in memory to provide the required bit stream for one input bit of the DAC. This work presents a half-rate 32 GSps MUX with 1 kbit built-in memory as a part of an arbitrary test signal generator for a DAC. The proposed system can be used to test DACs developed for future OFDM optical communications. Here, a bipolar-CMOS (BiCMOS) 0.25 μm SiGe process is utilised. One challenge is to optimise the power dissipation of such an MUX which requires employing several techniques. At the system level, the conventional tree structure was avoided because of the high number of latches required to re-time the clock and data signals. At the highest rates, a multiphase-clock architecture was utilised which halves the number of latches compared with a tree structure. The phase margin of the multiphase-clock structure is enhanced in this work. At lower rates, a one-stage MUX architecture was used which also halves the number of latches. Additionally, the latency between the analogue–digital interface is discussed. All the implemented circuits including the biasing of the whole chip and its routing are presented. The design and optimisation of the clock driver for low-power functionality is discussed. Measurement results show proper operation at 32 GSps. The total power dissipation is 875 mW, which is the lowest power among the designs usable for DAC testing and at the same rate class.

References

1. 1)
  - 24. Kim, J., Kim, J.K., Lee, B.J., Jeong, D.K.: ‘Design optimization of on-chip inductive peaking structures for 0.13-μm CMOS 40-Gb/s transmitter circuits’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2009, 56, (12), pp. 2544–2555 (doi: 10.1109/TCSI.2009.2023772).
2. 2)
  - 14. Khafaji, M., Carta, C., Sobotta, E., Micusik, D., Ellinger, F.: ‘An inductorless higher than 34 Gbit/s half-rate 4:1 multiplexer in 0.25-μm SiGe technology’. Ninth Conf. Ph.D. Research in Microelectronics and Electronics (PRIME), Villach, Austria; 2013, pp. 257–260.
3. 3)
  - 23. Yim, Y.U., Curran, P.F., Chu, M., McDonald, J.F., Kraft, R.P.: ‘52 Gb/s 16:1 transmitter in 0.13-μm SiGe BiCMOS technology’, IET Circuits, Devices Syst., 2007, 1, (6), pp. 427–432 (doi: 10.1049/iet-cds:20060320).
4. 4)
  - 11. Nadal, L., Svaluto Moreolo, M., Fabrega, J.M., Junyent, G.: ‘Clipping and quantization noise mitigation in intensity-modulated direct detection O-OFDM systems based on the FHT’. 2012 14th Int. Conf. Transparent Optical Networks (ICTON), 2012, pp. 1–4.
5. 5)
  - 19. Starič, P., Margan, E.: ‘Wideband amplifiers’ (Springer, Dordrecht, The Netherlands, 2007).
6. 6)
  - 8. Khafaji, M., Gustat, H., Sedighi, B., Ellinger, F., Scheytt, J.C.: ‘A 6-bit fully binary digital-to-analog converter in 0.25-μm SiGe BiCMOS for optical communications’, IEEE Trans. Microw. Tech., 2011, 59, (9), pp. 2254–2264 (doi: 10.1109/TMTT.2011.2161879).
7. 7)
  - 12. Razavi, B.: ‘Design of integrates circuits for optical communications’ (McGraw-Hill Series in Electrical and Computer Engineering Series. McGraw-Hill Higher Education, 2003, 1st edn.).
8. 8)
  - 23. Wei, J.L., Cunningham, D.G., Penty, R.V., White, I.H.: ‘Study of 100G Ethernet using carrierless amplitude/phase modulation and optical OFDM’, J. Lightwave Technol., 2013, 31, (9), pp. 1367–1373 (doi: 10.1109/JLT.2013.2248122).
9. 9)
  - 2. Baranauskas, D., Zelenin, D.: ‘A 0.36 W 6b up to 20 GS/s DAC for UWB wave formation’. IEEE Int. Solid-State Circuits Conf., Digest of Technical Papers, ISSCC, 2006, pp. 2380–2389.
10. 10)
  - 9. Nagatani, M., Nosaka, H., Yamanaka, S., Sano, K., Murata, K.: ‘Ultrahigh-speed low-power DACs using InP HBTs for beyond-100-Gb/s/ch optical transmission systems’, IEEE J. Solid-State Circuits, 2011, 46, (10), pp. 2215–2225 (doi: 10.1109/JSSC.2011.2163211).
11. 11)
  - 6. Kanda, K., Tamura, H., Yamamoto, T., et al: ‘A single-40 Gb/s dual-20 Gb/s serializer IC with SFI-5.2 interface in 65 nm CMOS’, IEEE J. Solid-State Circuits, 2009, 44, (12), pp. 3580–3589 (doi: 10.1109/JSSC.2009.2031030).
12. 12)
  - 16. Ishii, K., Nosaka, H., Ida, M., et al: ‘4-bit multiplexer/demultiplexer chip set for 40-Gbit/s optical communication systems’, IEEE Trans. Microw. Theory Tech., 2003, 51, (11), pp. 2181–2187 (doi: 10.1109/TMTT.2003.818582).
13. 13)
  - 17. Gray, P.R., Hurst, P.J., Lewis, S.H., Meyer, R.G.: ‘Analysis and design of analog integrated circuits’ (John Wiley & Sons, Inc., New York, 2001, 4th edn.).
14. 14)
  - 20. Holdenried, C.D., Haslett, J.W., Lynch, M.W.: ‘Analysis and design of HBT Cherry–Hooper amplifiers with emitter-follower feedback for optical communications’, IEEE J. Solid-State Circuits, 2004, 39, (11), pp. 1959–1967 (doi: 10.1109/JSSC.2004.835819).
15. 15)
  - 4. Ellermeyer, T., Mullrich, J., Rupeter, J., Langenhagen, H., Bielik, A., Moller, M.: ‘DA and AD converters for 25 GS/s and above’. Digest of the IEEE/LEOS Summer Topical Meetings, 2008, pp. 117–118.
16. 16)
  - 1. Schvan, P., Pollex, D., Bellingrath, T.: ‘A 22GS/s 6b DAC with integrated digital ramp generator’. IEEE Int. Solid-State Circuits Conf., Digest of Technical Papers, ISSCC, 2005, pp. 122–588.
17. 17)
  - 18. Veenstra, H., Long, J.R.: ‘Circuit and interconnect design for high bit-rate applications’ (Springer Science + Business Media B.V., USA, 2008, 1st edn.).
18. 18)
  - 5. Alpert, T., Werz, M., Lang, F., et al: ‘Arbitrary waveform generator based on FPGA and high-speed DAC with real-time interface’. Eighth Conf. Ph.D. Research in Microelectronics and Electronics (PRIME), Aachen, Germany, 2012, pp. 1–4.
19. 19)
  - 15. Kehrer, D., Wohlmuth, H.D.: ‘A 30-Gb/s 70-mW one-stage 4:1 multiplexer in 0.13-μm CMOS’, IEEE J. Solid-State Circuits, 2004, 39, (7), pp. 1140–1147 (doi: 10.1109/JSSC.2004.829397).
20. 20)
  - 7. Kaeriyama, S., Amamiya, Y., Noguchi, H., et al: ‘A 40 Gb/s multi-data-rate CMOS transmitter and receiver chipset with SFI-5 interface for optical transmission systems’, IEEE J. Solid-State Circuits, 2009, 44, (12), pp. 3568–3579 (doi: 10.1109/JSSC.2009.2031026).
21. 21)
  - 22. Tsai, W.Y., Chiu, C.T., Wu, J.M., Hsu, S.S.H., Hsu, Y.S.: ‘A novel low gate-count pipeline topology with multiplexer-flip-flop for serial link’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2012, 59, (11), pp. 2600–2610 (doi: 10.1109/TCSI.2012.2206494).
22. 22)
  - 13. Suzuki, T., Kawano, Y., Nakasha, Y., et al: ‘A 50-Gbit/s 450-mW full-rate 4:1 multiplexer with multiphase clock architecture in 0.13-μm InP HEMT technology’, IEEE J. Solid-State Circuits, 2007, 42, (3), pp. 637–646 (doi: 10.1109/JSSC.2006.891495).
23. 23)
  - 3. Greshishchev, Y.M., Pollex, D., Wang, S.C., et al: ‘A 56GS/S 6b DAC in 65 nm CMOS with 256 × 6b memory’. IEEE Int. Solid-State Circuits Conf., Digest of Technical Papers, ISSCC, 2011, pp. 194–196.
24. 24)
  - 21. Steyaert, M.S.J., Bijker, W., Vorenkamp, P., Sevenhans, J.: ‘ECL-CMOS and CMOS-ECL interface in 1.2-μm CMOS for 150-MHz digital ECL data transmission systems’, IEEE J. Solid-State Circuits, 1991, 26, (1), pp. 18–24 (doi: 10.1109/4.65705).

A 32 GSps multiplexer with 1 kbit memory for arbitrary signal generation for testing digital-to-analogue converters

References

Related content