This study presents a full methodological approach to designing and verifying differential sample and hold switched-capacitor circuits generally used in analogue-to-digital converters (ADCs). It provides a step-by-step process for translating system requirements such as signal-to-noise ratio and sampling frequency into ADC requirements and subsequently into operational amplifier topology and specifications. It also includes the design process of a switched-capacitor common mode feedback circuit to control the common mode output voltage. Furthermore, this study discusses the noise aspects of the switched-capacitor circuits. It also provides practical methods for verifying the stability of the system by using step voltage and step current techniques. A design and simulation example for a differential sample and hold switched-capacitor circuit operating in a system requiring a 5 MHz sampling frequency and a 6-bit ADC is provided. Mentor Graphics CAD tools were used in the design and the simulations process by using 180 nm complementary metal oxide semiconductors (CMOS) device models. This study can be used as a resource for the design engineers in the industry as well as the universities teaching graduate level advanced electronics and data converter courses.

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Methodology for designing and verifying switched-capacitor sample and hold circuits used in data converters

References

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