This study presents a new spur reducing architecture of phase-locked loop-based frequency synthesiser. In the proposed architecture, an array of switched capacitors and a delay locked loop are used to evenly transfer the charge, coming from its charge pump, to its loop filter at a fixed number of equi-spaced time intervals. It reduces fundamental as well as higher-order harmonics of the reference spur. The proposed architecture has been designed and fabricated using 180 nm complementary metal oxide semiconductor technology. Measured result shows about 17.64 dB reduction of the fundamental spur compared with that of the conventional architecture.

References

1. 1)
  - 12. Elsayed, M.M., Abdul-Latif, M., Sanchez-Sinencio, E.: ‘A spur-frequency-boosting PLL with a −74 dBc reference-spur suppression in 90 nm digital CMOS’, IEEE J. Solid-State Circuits, 2013, 48, (9), pp. 2104–2117 (doi: 10.1109/JSSC.2013.2266865).
2. 2)
  - 13. Lee, T.-C., Lee, W.-L.: ‘A spur suppression technique for phase-locked frequency synthesizers’. IEEE Int. Solid-State Circuits Conf., February 2006, pp. 2432–2441.
3. 3)
  - M.S. Hwang , J. Kim , D.K. Jeong . Reduction of pump current mismatch in charge-pump PLL. Electron. Lett. , 3 , 135 - 136
4. 4)
  - 14. Thambidurai, C., Krishnapura, N.: ‘On pulse position modulation and its application to PLLs for spur reduction’, IEEE Trans. Circuits Syst. I, Regul. Pap., 2011, 58, (7), pp. 1483–1496 (doi: 10.1109/TCSI.2011.2157749).
5. 5)
  - W.B. Wilson . A CMOS self-calibrating frequency synthesizer. IEEE J. Solid-State Circuits , 1437 - 1444
6. 6)
  - P.K. Hanumolu , M. Brownlee , K. Mayaram , U.K. Moon . Analysis of charge pump phase locked loops. IEEE Trans. Circuit Syst.-I , 9 , 1665 - 1674
7. 7)
  - 7. Liang, C.-F., Chen, S.-H., Liu, S.-I.: ‘A digital calibration technique for charge pumps in phase-locked systems’, IEEE J. Solid-State Circuits, 2008, 43, (2), pp. 390–398 (doi: 10.1109/JSSC.2007.914283).
8. 8)
  - 2. Kuo, C.-Y., Chang, J.-Y., Liu, S.-I.: ‘A spur-reduction technique for a 5-GHz frequency synthesizer’, IEEE Trans. Circuits Syst. I Regul. Pap., 2006, 53, (3), pp. 526–533 (doi: 10.1109/TCSI.2005.858322).
9. 9)
  - 21. ZigBee Specifications: ‘IEEE Std. 802.15.4’, 2006.
10. 10)
  - 5. Gierkink, S.L.J.: ‘Low-spur, low-phase-noise clock multiplier based on a combination of PLL and recirculating DLL with dual-pulse ring oscillator and self-correcting charge pump’, IEEE J. Solid-State Circuits, 2008, 43, (12), pp. 2967–2976 (doi: 10.1109/JSSC.2008.2006225).
11. 11)
  - 1. Razavi, B.: ‘Challenges in the design of frequency synthesizers for wireless applications’. Proc. IEEE Custom Integrated Circuits Conf., May 1997, pp. 395–402.
12. 12)
  - 9. Zhang, G.: ‘Linearised charge pump independent of current mismatch through timing rearrangement’, Electron. Lett., 2010, 46, (1), pp. 33–34 (doi: 10.1049/el.2010.2555).
13. 13)
  - 4. Cho, S.H., Lee, H.D., Kim, K.-D., Ryu, S.T., Kwon, J.-K.: ‘Dual-mode VCO gain topology for reducing in-band noise and reference spur of PLL in 65 nm CMOS’, Electron. Lett., 2010, 46, (5), pp. 335–337 (doi: 10.1049/el.2010.3553).
14. 14)
  - 15. Choi, J., Kim, W., Lim, K.: ‘A spur suppression technique using an edge-interpolator for a charge-pump PLL’, IEEE Trans. Very Large Scale Integr. Syst., 2012, 20, (5), pp. 969–973.
15. 15)
  - 18. Fahs, B., Ali-Ahmad, W.Y., Gamand, P.: ‘A two-stage ring oscillator in 0.13-μm CMOS for UWB impulse radio’, IEEE Trans. Microw. Theory Tech., 2009, 57, (5), pp. 1074–1082 (doi: 10.1109/TMTT.2009.2017246).
16. 16)
  - 11. Liang, C.-F., Chen, H.-H., Liu, S.-I.: ‘Spur-suppression techniques for frequency synthesizers’, IEEE Trans. Circuits Syst. II, Express Briefs, 2007, 54, (8), pp. 653–657 (doi: 10.1109/TCSII.2007.896938).
17. 17)
  - 3. Mandal, D., Bhattacharyya, T.K.: ‘A technique to improve the linearization of frequency-voltage characteristic of LC-VCO’, Analog Integr. Circuits Signal Process., 2010, 62, (2), pp. 253–257 (doi: 10.1007/s10470-009-9380-0).
18. 18)
  - 19. Gardner, F.M.: ‘Phaselock techniques’ (John Wiley & Sons, Inc., 3rd edn.).
19. 19)
  - C.S. Vaucher , I. Ferencic , M. Locher , S. Sedvallson , U. Voegeli , Z. Wang . A family of low-power truly modular programmable dividers in standard 0.35-μm CMOS technology. IEEE J. Solid-State Circuits , 7 , 1039 - 1045
20. 20)
  - 6. Charles, C.T., Allstot, D.J.: ‘A calibrated phase/frequency detector for reference spur reduction in charge-pump PLLs’, IEEE Trans. Circuits Syst. II, Express Briefs, 2006, 53, (9), pp. 822–826 (doi: 10.1109/TCSII.2006.880030).
21. 21)
  - 10. Yun, S.-J., Lee, H.D., Kim, K.-D., Kwon, J.-K.: ‘Differentially-tuned low-spur PLL using 65 nm CMOS process’, Electron. Lett., 2011, 47, (6), pp. 369–371 (doi: 10.1049/el.2011.0166).
22. 22)
  - 17. Mandal, D., Mandal, P., Bhattacharyya, T.K.: ‘Spur suppression in frequency synthesizer using switched capacitor array’. Int. System-on-Chip (SoC) Design Conf., November 2012, pp. 100–103.

Spur reducing architecture of frequency synthesiser using switched capacitors

References

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