Spur reducing architecture of frequency synthesiser using switched capacitors
- Author(s): Debashis Mandal 1 ; Pradip Mandal 1 ; Tarun Kanti Bhattacharyya 1
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Affiliations:
1:
Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur 721302, India
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Affiliations:
1:
Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur 721302, India
- Source:
Volume 8, Issue 4,
July 2014,
p.
237 – 245
DOI: 10.1049/iet-cds.2013.0200 , Print ISSN 1751-858X, Online ISSN 1751-8598
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This study presents a new spur reducing architecture of phase-locked loop-based frequency synthesiser. In the proposed architecture, an array of switched capacitors and a delay locked loop are used to evenly transfer the charge, coming from its charge pump, to its loop filter at a fixed number of equi-spaced time intervals. It reduces fundamental as well as higher-order harmonics of the reference spur. The proposed architecture has been designed and fabricated using 180 nm complementary metal oxide semiconductor technology. Measured result shows about 17.64 dB reduction of the fundamental spur compared with that of the conventional architecture.
Inspec keywords: charge pump circuits; CMOS integrated circuits; frequency synthesizers; switched capacitor networks; phase locked loops; delay lock loops
Other keywords: spur reducing architecture; charge pump; equi-spaced time intervals; complementary metal oxide semiconductor technology; phase locked loop; higher-order harmonics; loop filter; size 180 nm; frequency synthesiser; switched capacitors; delay locked loop
Subjects: Power electronics, supply and supervisory circuits; Other digital circuits; CMOS integrated circuits; Signal generators; Time varying and switched networks; Other analogue circuits; Modulators, demodulators, discriminators and mixers
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