access icon free Development of low-complexity all-digital frequency locked loop as 500 MHz reference clock generator for field-programmable gate array

The authors report the development of an on-chip 500 MHz reference clock generator as a part of a clock manager for a field-programmable gate array. The generator is implemented in the form of an all-digital frequency locked loop (ADFLL) in architecture of low complexity and high modularity. For the development of the ADFLL, they propose a new circuit that employs two under-sampled 1-bit ΔΣ frequency-to-digital converters to convert a frequency difference into a proportional distributed pulsewidth. By the combination of the proposed circuit with a conventional phase-and-frequency detector, a frequency comparator is implemented and can indicate its two input frequency conditions, that is, (i) equal to, (ii) lower than or (iii) higher than. The ADFLL which adopts the proposed frequency comparator is implemented in a 90 nm CMOS technology. Consuming 2.64 mW from a 1.2 V supply, the ADFLL shows about 50 µs of locking time at the frequency accuracy of 99.2% while operating at 500 MHz and being driven by a 10 MHz reference clock.

Inspec keywords: CMOS logic circuits; reference circuits; comparators (circuits); delta-sigma modulation; phase detectors; field programmable gate arrays; frequency locked loops

Other keywords: distributed pulsewidth; low-complexity all-digital frequency locked loop; under-sampled ΔΣ frequency-to-digital converters; ADFLL; field-programmable gate array; CMOS technology; on-chip reference clock generator; power 2.64 mW; voltage 1.2 V; phase-and-frequency detector; frequency 500 MHz; word length 1 bit; size 90 nm; frequency comparator

Subjects: CMOS integrated circuits; Logic circuits; Power electronics, supply and supervisory circuits; Other analogue circuits; Logic and switching circuits; Modulators, demodulators, discriminators and mixers; A/D and D/A convertors; A/D and D/A convertors

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