© The Institution of Engineering and Technology
The authors report the development of an on-chip 500 MHz reference clock generator as a part of a clock manager for a field-programmable gate array. The generator is implemented in the form of an all-digital frequency locked loop (ADFLL) in architecture of low complexity and high modularity. For the development of the ADFLL, they propose a new circuit that employs two under-sampled 1-bit ΔΣ frequency-to-digital converters to convert a frequency difference into a proportional distributed pulsewidth. By the combination of the proposed circuit with a conventional phase-and-frequency detector, a frequency comparator is implemented and can indicate its two input frequency conditions, that is, (i) equal to, (ii) lower than or (iii) higher than. The ADFLL which adopts the proposed frequency comparator is implemented in a 90 nm CMOS technology. Consuming 2.64 mW from a 1.2 V supply, the ADFLL shows about 50 µs of locking time at the frequency accuracy of 99.2% while operating at 500 MHz and being driven by a 10 MHz reference clock.
References
-
-
1)
-
10. Olsson, T., Nilsson, P.: ‘A fully integrated standard-cell digital PLL’, IEE Electron. Lett., 2001, 37, pp. 211–212 (doi: 10.1049/el:20010160).
-
2)
-
8. Okada, T., Endo, A.: ‘Digital frequency comparator circuit’. .
-
3)
-
S.-K. Lee
.
A 1 GHz ADPLL with a 1.25 ps minimum-resolution sub exponent TDC in 0.18 µm CMOS.
IEEE J. Solid-State Circuits
,
12 ,
2874 -
2881
-
4)
-
15. Mesgarzadeh, B., Alvandpour, A.: ‘A low-power digital DLL-based clock generator in open-loop mode’, IEEE J. Solid-State Circuits, 2009, 44, (7), pp. 1907–1913 (doi: 10.1109/JSSC.2009.2020229).
-
5)
-
Y.C. Yang ,
S.A. Yu ,
T. Wang ,
S.S. Lu
.
A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell.
IEEE Microw. Wirel. Compon. Lett.
,
11 ,
754 -
756
-
6)
-
6. Wang, C.-C., Huang, C.-C., Tseng, S.-L.: ‘A low-power ADPLL using feedback DCO quarterly disabled in time domain’, Microelectron. J., 2008, 39, (5), pp. 832–840 (doi: 10.1016/j.mejo.2007.12.029).
-
7)
-
4. Kratyuk, V., Hanumolu, P., Moon, U., Mayaram, K.: ‘All-digital phase-locked loops based on a charge-pump phase-locked-loop analogy’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2007, 54, (3), pp. 247–251 (doi: 10.1109/TCSII.2006.889443).
-
8)
-
K.-H. Choi ,
J.-B. Shin ,
J.-Y. Sim ,
H.-J. Park
.
An interpolating digitally controlled oscillator for a wide-range all-digital PLL.
IEEE Trans. Circuits Syst. I, Regular Papers
,
9 ,
2055 -
2063
-
9)
-
10)
-
12. Javeri, R.J., Grove, E.: ‘Frequency substractor’. .
-
11)
-
M. Hovin ,
A. Olsen ,
T.S. Lande ,
C. Toumazou
.
Delta-sigma modulators using frequency-modulated intermediate values.
IEEE J. Solid-State Circuits
,
13 -
22
-
12)
-
J.A. Tierno
.
A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI.
IEEE J. Solid-State Circuits
,
42 -
51
-
13)
-
5. Khalil, W., Shashidharan, S., Copani, T., et al: ‘A 700-µA 405-MHz all-digital fractional-N frequency- locked loop for ISM band applications’, IEEE Trans. Microw. Theory Tech., 2011, 59, (5), pp. 1319–1326 (doi: 10.1109/TMTT.2011.2114897).
-
14)
-
4. Kratyuk, V., Hanumolu, P., Moon, U., Mayaram, K.: ‘All-digital phase-locked loops based on a charge-pump phase-locked-loop analogy’, IEEE Trans. Circuits Syst. II, Exp. Briefs, 2007, 54, (3), pp. 247–251 (doi: 10.1109/TCSII.2006.889443).
-
15)
-
1. Manassewitsch, V.: ‘Frequency synthesizers: theory and design’ (Wiley-Interscience, New York, 1980, 2nd edn.), pp. 22–31.
-
16)
-
3. Gothandaraman, A., Islam, S.K.: ‘An all-digital frequency locked loop (ADFLL) with a pulse output direct digital frequency synthesizer (DDFS) and an adaptive phase estimator’. Proc. RFIC Symp., Philadelphia, PA, USA, June 2003, pp. 303–306.
-
17)
-
16. Lee, S., Seo, Y., Park, H., Sim, J.: ‘A 1 GHz ADPLL with a 1.25 ps minimum-resolution sub-exponent TDC in 0.18 µm CMOS’, IEEE J. Solid-State Circuits, 2010, 45, (12), pp. 2874–2882 (doi: 10.1109/JSSC.2010.2077110).
-
18)
-
11. Tierno, J., Rylyakov, A., Friedman, D.: ‘A wide power supply range, wide tuning range, all static CMOS all digital PLL in 65 nm SOI’, IEEE J. Solid-State Circuits, 2008, 43, (1), pp. 42–51 (doi: 10.1109/JSSC.2007.910966).
-
19)
-
6. Wang, C.-C., Huang, C.-C., Tseng, S.-L.: ‘A low-power ADPLL using feedback DCO quarterly disabled in time domain’, Microelectron. J., 2008, 39, (5), pp. 832–840 (doi: 10.1016/j.mejo.2007.12.029).
-
20)
-
18. Choi, K.-H., Shin, J.-B., Sim, J.-Y., Park, H.-J.: ‘An interpolating digitally controlled oscillator for a wide-range all-digital PLL’, IEEE Trans. Circuits Syst. I, Reg. Pap., 2009, 56, (9), pp. 2055–2063 (doi: 10.1109/TCSI.2008.2011577).
-
21)
-
2. Zhuang, J., Du, Q., Kwasniewski, T.: ‘A 4 GHz low complexity ADPLL-based frequency synthesizer in 90 nm CMOS’. Proc. IEEE CICC, San Jose, CA, USA, September 2007, pp. 543–546.
-
22)
-
13. Hovin, M., Olsen, A., Lande, T.S., Toumazou, C.: ‘Delta-sigma modulators using frequency modulated intermediate values’, IEEE J. Solid-State Circuits, 1997, 32, pp. 13–22 (doi: 10.1109/4.553171).
-
23)
-
10. Olsson, T., Nilsson, P.: ‘A fully integrated standard-cell digital PLL’, IEE Electron. Lett., 2001, 37, pp. 211–212 (doi: 10.1049/el:20010160).
-
24)
-
5. Khalil, W., Shashidharan, S., Copani, T., et al: ‘A 700-µA 405-MHz all-digital fractional-N frequency- locked loop for ISM band applications’, IEEE Trans. Microw. Theory Tech., 2011, 59, (5), pp. 1319–1326 (doi: 10.1109/TMTT.2011.2114897).
-
25)
-
26)
-
14. Hovin, M., Saether, T., Wisland, D.T., Lande, T.S.: ‘A narrow-band delta-sigma frequency-to-digital converter’. Proc. IEEE ISCAS, Hong Kong, June 1997, vol. 1, pp. 77–80.
-
27)
-
12. Javeri, R.J., Grove, E.: ‘Frequency substractor’. , 28 July 1987.
-
28)
-
8. Okada, T., Endo, A.: ‘Digital frequency comparator circuit’. , 19 October 1976.
-
29)
-
15. Mesgarzadeh, B., Alvandpour, A.: ‘A low-power digital DLL-based clock generator in open-loop mode’, IEEE J. Solid-State Circuits, 2009, 44, (7), pp. 1907–1913 (doi: 10.1109/JSSC.2009.2020229).
-
30)
-
17. Banerjee, D.: ‘PLL performance, simulation, and design’ (Dog Ear Publishing, Indianapolis, 2006, 4th edn.), pp. 64–72.
-
31)
-
9. Yang, Y.-C., Yu, S.-A., Wang, T., Lu, S.-S.: ‘A dual-mode truly modular programmable fractional divider based on a 1/1.5 divider cell’, IEEE Microw. Wirel. Compon. Lett., 2005, 15, (11), pp. 754–756 (doi: 10.1109/LMWC.2005.858978).
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2013.0175
Related content
content/journals/10.1049/iet-cds.2013.0175
pub_keyword,iet_inspecKeyword,pub_concept
6
6