access icon free On-chip readout circuit for nanomagnetic logic

© The Institution of Engineering and Technology
Received 06/09/2012, Accepted 03/08/2013, Revised 22/07/2013, Published

An interface for reading the output of nanomagnetic logic (NML) is indispensable in order for NML to interact with existing CMOS ICs. Two alternative designs readout interface circuit (RIC1 and RIC2) for NML RIC are proposed based on dual barriers magnetic tunnel junction (DBs-MTJ), which is composed of two fixed layers (with anti-parallel magnetisation state) and a common free layer. RIC1 utilises the same layer order of DB-MTJ to form an up–down structure, whereas RIC2 exploits the reversed layer order of DB-MTJ to form a left–right structure. They utilise the three-terminal approach to realise the self-reference readout scheme. The magnetisation state of the free layers in RIC1 and RIC2 are controlled by the fringing field from NML and biased by the designed on-chip clock field. The sensing circuits in RIC1 and RIC2 utilise dynamic current mode and pre-charge sense amplifier, respectively. The simulation results indicate that RIC1 and RIC2 can achieve comparable magnetoresistance values, and also realise the logical readout scheme by itself. The switching time in RIC1 is less than that in RIC2, whereas time delay for data transportation in RIC1 is more than that in RIC2. RIC2 is more amenable than RIC1 to the current fabrication process technology.

Inspec keywords: nanomagnetics; delays; preamplifiers; CMOS logic circuits; magnetisation; magnetoresistance; readout electronics

Other keywords: on-chip readout circuit; time delay; antiparallel magnetisation state; up-down structure; dual barrier magnetic tunnel junction; RIC2; self-reference readout scheme; magnetoresistance value; nanomagnetic logic; NML; on-chip clock fleld; NML RIC; dynamic current mode; fringing fleld; left-right structure; precharge sense amplifler; magnetisation state; data transportation; logical readout scheme; three-terminal approach; DB-MTJ; fabrication process technology; readout interface circuit

Subjects: Magnetic materials; Amplifiers; Logic circuits; Logic and switching circuits; CMOS integrated circuits; Power electronics, supply and supervisory circuits

References

    1. 1)
      • 25. Feng, J.F., Feng, G., Ma, Q.L., Han, X.F., Coey, J.M.D.: ‘Temperature dependence of inverted tunneling magnetoresistance in MgO-based magnetic tunnel junctions’, J. Magn. Magn. Mater., 2010, 322, pp. 1446–1448, (doi: 10.1016/j.jmmm.2009.04.072).
    2. 2)
      • 23. You, C.-Y., Han, J.-H., Lee, H.-W.: ‘Spin transfer torque and tunneling magnetoresistance dependences on finite bias voltages and insulator barrier energy’, Thin Solid Films, 2011, 519, pp. 8247–8251, (doi: 10.1016/j.tsf.2011.03.057).
    3. 3)
      • 26. Zhao, W.S., Zhang, Y., Devolder, T., et al: ‘Failure and reliability analysis of STT-MARM’, Microelectron. Reliab., 2012, 52, pp. 1848–1852, (doi: 10.1016/j.microrel.2012.06.035).
    4. 4)
      • 3. Orlov, A., Imre, A., Csaba, G., Ji, L., Porod, W., Bernstein, G.H.: ‘Magnetic quantum-dot cellular automata: recent developments and prospects’, J. Nanoelectron. Optoelectron., 2008, 3, pp. 1–14, (doi: 10.1166/jno.2008.004).
    5. 5)
      • 5. Alam, M.T., Kurtz, S.J., Siddiq, M.A.J., et al: ‘On-chip clocking of nanomagnet logic lines and gates’, IEEE Trans. Nanotechnol., 2012, 11, pp. 273–286, (doi: 10.1109/TNANO.2011.2169983).
    6. 6)
      • 22. Gang, Y., Zhao, W., Klein, J.O., Chappert, C., Mazoyer, P.: ‘A high-reliability, low-power magnetic full adder’, IEEE Trans. Magn., 2011, 47, pp. 4611–4616, (doi: 10.1109/TMAG.2011.2150238).
    7. 7)
      • 7. Csaba, G., Porod, W., Csurgay, A.I.: ‘A computing architecture composed of field-coupled single domain nanomagnets clocked by magnetic field’, Int. J. Circ. Theory Appl., 2003, 31, pp. 67–82, (doi: 10.1002/cta.226).
    8. 8)
      • 2. Liu, S., Hu, X.S., Nahas, J.J., Niemier, M.T., Porod, W., Bernstein, G.H.: ‘Magnetic-electrical interface for nanomagnet logic’, IEEE Trans. Nanotechnol., 2011, 10, pp. 757–763. (doi: 10.1109/TNANO.2010.2077645).
    9. 9)
      • 18. Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., Zhang, T.: ‘A 130 nm 1.2 V/3.3 V 16 Kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme’, IEEE J. Solid-State Circuits, 2012, 47, pp. 560–573, (doi: 10.1109/JSSC.2011.2170778).
    10. 10)
      • 10. Becherer, M., Kiermaier, J., Breitkreutz, S., et al: ‘On-chip extraordinary Hall-effect sensors for characterization of nanomagnetic logic devices’, Solid-State Electron., 2010, 54, pp. 1027–1032, (doi: 10.1016/j.sse.2010.04.011).
    11. 11)
      • 27. Maheshwari, A., Burleson, W., Tessier, R.: ‘Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits’, IEEE Trans. VLSI Syst., 2004, 12, pp. 299–311, (doi: 10.1109/TVLSI.2004.824302).
    12. 12)
      • 15. Tsymbal, E.Y., Mryasov, O.N., LeClair, P.R.: ‘Spin-dependent tunneling in magnetic tunnel junctions’, J. Phys.: Condens. Matter, 2003, 15, pp. R109–R142, (doi: 10.1088/0953-8984/15/4/201).
    13. 13)
      • 19. Braganca, P.M., Katine, J.A., Emley, N.C., et al: ‘A three-terminal approach to developing spin-torque written magnetic random access memory cells’, IEEE Trans. Nanotechnol., 2009, 8, pp. 190–195, (doi: 10.1109/TNANO.2008.2005187).
    14. 14)
      • 21. Zhao, W., Chappert, C., Javerliac, V., Noziere, J.P.: ‘High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits’, IEEE Trans. Magn., 2009, 45, pp. 3784–3787, (doi: 10.1109/TMAG.2009.2024325).
    15. 15)
      • 1. Wilson, L.: ‘International technology roadmap for semiconductors: emerging research devices’(2009en, 2009th edn.), Available at http://www.itrs.net.
    16. 16)
      • 6. Alam, M.T., Siddiq, M.J., Bernstein, G.H., Niemier, M., Porod, W., Hu, X.S.: ‘On-chip clocking for nanomagnet logic devices’, IEEE Trans. Nanotechnol., 2010, 9, pp. 348–351, (doi: 10.1109/TNANO.2010.2041248).
    17. 17)
      • 16. Zhao, W.S., Devolder, T., Lakys, Y., Klein, J.O., Chappet, C., Mazoyer, P.: ‘Design considerations and strategies for high-reliable STT-MARM’, Microelectron. Reliab., 2011, 51, pp. 1454–1458, (doi: 10.1016/j.microrel.2011.07.001).
    18. 18)
      • 20. Augustine, C., Raychowdhury, A., Somasekhar, D., Tschanz, J., De, V., Roy, K.: ‘Design space exploration of typical STT MTJ stacks in memory arrays in the presence of variability and disturbances’, IEEE Trans. Electron Devices, 2011, 58, pp. 4333–4343, (doi: 10.1109/TED.2011.2169962).
    19. 19)
      • 17. Zhang, Y., Zhao, W., Lakys, Y., et al: ‘Compact modeling of perpendicular- anisotropy CoFeB/MgO magnetic tunnel junctions’, IEEE Trans. Electron Devices, 2012, 59, pp. 819–826, (doi: 10.1109/TED.2011.2178416).
    20. 20)
      • 24. Yuasa, S., Nagahama, T., Fukushima, A., Suzuki, Y., Ando, A.K.: ‘Giant room-temperature magnetoresistance in single-crystal Fe/MgO/Fe magnetic tunneling junctions’, Nat. Mater., 2004, 3, pp. 868–871, (doi: 10.1038/nmat1257).
    21. 21)
      • 4. Imre, A., Csaba, G., Ji, L., Orlov, A., Bernstein, G.H., Porod, W.: ‘Majority logic gate for magnetic quantum-dot cellular automata’, Science, 2006, 311, pp. 205–208, (doi: 10.1126/science.1120506).
    22. 22)
      • 25. Feng, J.F., Feng, G., Ma, Q.L., Han, X.F., Coey, J.M.D.: ‘Temperature dependence of inverted tunneling magnetoresistance in MgO-based magnetic tunnel junctions’, J. Magn. Magn. Mater., 2010, 322, pp. 1446–1448, (doi:10.1016/j.jmmm.2009.04.072) (doi: 10.1016/j.jmmm.2009.04.072).
    23. 23)
      • 24. Yuasa, S., Nagahama, T., Fukushima, A., Suzuki, Y., Ando, A.K.: ‘Giant room-temperature magnetoresistance in single-crystal Fe/MgO/Fe magnetic tunneling junctions’, Nat. Mater., 2004, 3, pp. 868–871, (doi:10.1038/nmat1257) (doi: 10.1038/nmat1257).
    24. 24)
      • 17. Zhang, Y., Zhao, W., Lakys, Y., et al: ‘Compact modeling of perpendicular- anisotropy CoFeB/MgO magnetic tunnel junctions’, IEEE Trans. Electron Devices, 2012, 59, pp. 819–826, (doi: 10.1109/TED.2011.2178416) (doi: 10.1109/TED.2011.2178416).
    25. 25)
      • 12. Zhu, J., Park, C.: ‘Magnetic tunnel junctions’, Mater. Today, 2006, 9, pp. 36–45 (doi: 10.1016/S1369-7021(06)71693-5).
    26. 26)
      • 10. Becherer, M., Kiermaier, J., Breitkreutz, S., et al: ‘On-chip extraordinary Hall-effect sensors for characterization of nanomagnetic logic devices’, Solid-State Electron., 2010, 54, pp. 1027–1032, (doi: 10.1016/j.sse.2010.04.011) (doi: 10.1016/j.sse.2010.04.011).
    27. 27)
      • 14. Maffitt, T.M., DeBrosse, J.K., Gabric, J.A., et al: ‘Design considerations for MRAM’, IBM J. Res. Dev., 2006, 50, pp. 25–39 (doi: 10.1147/rd.501.0025).
    28. 28)
      • 4. Imre, A., Csaba, G., Ji, L., Orlov, A., Bernstein, G.H., Porod, W.: ‘Majority logic gate for magnetic quantum-dot cellular automata’, Science, 2006, 311, pp. 205–208, (doi: 10.1126/science.1120506) (doi: 10.1126/science.1120506).
    29. 29)
      • 20. Augustine, C., Raychowdhury, A., Somasekhar, D., Tschanz, J., De, V., Roy, K.: ‘Design space exploration of typical STT MTJ stacks in memory arrays in the presence of variability and disturbances’, IEEE Trans. Electron Devices, 2011, 58, pp. 4333–4343, (doi: 10.1109/TED.2011.2169962) (doi: 10.1109/TED.2011.2169962).
    30. 30)
      • 5. Alam, M.T., Kurtz, S.J., Siddiq, M.A.J., et al: ‘On-chip clocking of nanomagnet logic lines and gates’, IEEE Trans. Nanotechnol., 2012, 11, pp. 273–286, (doi: 10.1109/TNANO.2011.2169983) (doi: 10.1109/TNANO.2011.2169983).
    31. 31)
      • 16. Zhao, W.S., Devolder, T., Lakys, Y., Klein, J.O., Chappet, C., Mazoyer, P.: ‘Design considerations and strategies for high-reliable STT-MARM’, Microelectron. Reliab., 2011, 51, pp. 1454–1458, (doi:10.1016/j.microrel.2011.07.001) (doi: 10.1016/j.microrel.2011.07.001).
    32. 32)
      • 22. Gang, Y., Zhao, W., Klein, J.O., Chappert, C., Mazoyer, P.: ‘A high-reliability, low-power magnetic full adder’, IEEE Trans. Magn., 2011, 47, pp. 4611–4616, (doi: 10.1109/TMAG.2011.2150238) (doi: 10.1109/TMAG.2011.2150238).
    33. 33)
      • 23. You, C.-Y., Han, J.-H., Lee, H.-W.: ‘Spin transfer torque and tunneling magnetoresistance dependences on finite bias voltages and insulator barrier energy’, Thin Solid Films, 2011, 519, pp. 8247–8251, (doi:10.1016/j.tsf.2011.03.057) (doi: 10.1016/j.tsf.2011.03.057).
    34. 34)
      • 21. Zhao, W., Chappert, C., Javerliac, V., Noziere, J.P.: ‘High speed, high stability and low power sensing amplifier for MTJ/CMOS hybrid logic circuits’, IEEE Trans. Magn., 2009, 45, pp. 3784–3787, (doi: 10.1109/TMAG.2009.2024325) (doi: 10.1109/TMAG.2009.2024325).
    35. 35)
      • 26. Zhao, W.S., Zhang, Y., Devolder, T., et al: ‘Failure and reliability analysis of STT-MARM’, Microelectron. Reliab., 2012, 52, pp. 1848–1852, (doi: 10.1016/j.microrel.2012.06.035) (doi: 10.1016/j.microrel.2012.06.035).
    36. 36)
      • 8. Alam, M.T., DeAngelis, J., Putney, M., et al: ‘Clocking scheme for nanomagnet QCA’. Proc. Seventh IEEE Int. Conf. Nanotechnology2007, pp. 403–408.
    37. 37)
      • 18. Chen, Y., Li, H., Wang, X., Zhu, W., Xu, W., Zhang, T.: ‘A 130 nm 1.2 V/3.3 V 16 Kb spin-transfer torque random access memory with nondestructive self-reference sensing scheme’, IEEE J. Solid-State Circuits, 2012, 47, pp. 560–573, (doi: 10.1109/JSSC.2011.2170778) (doi: 10.1109/JSSC.2011.2170778).
    38. 38)
      • 27. Maheshwari, A., Burleson, W., Tessier, R.: ‘Trading off transient fault tolerance and power consumption in deep submicron (DSM) VLSI circuits’, IEEE Trans. VLSI Syst., 2004, 12, pp. 299–311, (doi: 10.1109/TVLSI.2004.824302) (doi: 10.1109/TVLSI.2004.824302).
    39. 39)
      • 15. Tsymbal, E.Y., Mryasov, O.N., LeClair, P.R.: ‘Spin-dependent tunneling in magnetic tunnel junctions’, J. Phys.: Condens. Matter, 2003, 15, pp. R109–R142, (doi: 10.1088/0953-8984/15/4/201) (doi: 10.1088/0953-8984/15/4/201).
    40. 40)
      • 9. Becherer, M., Kiermaier, J., Csaba, G., et al: ‘Characterizing magnetic field-coupled computing devices by the extraordinary Hall-effect’. IEEE Proc. 39th European Solid-State Device Research Conf., ESSDERC, 2009, pp. 105–108.
    41. 41)
      • 11. Zhao, W., Belhaire, E., Mistral, Q., Javerliac, V., Dieny, B., Nicolle, E.: ‘Macro-model of spin-transfer torque based magnetic tunnel junction device for hybrid magnetic-CMOS design’. IEEE Int. Behavior Modeling and Simulation Workshop, 2006, pp. 40–43.
    42. 42)
      • 6. Alam, M.T., Siddiq, M.J., Bernstein, G.H., Niemier, M., Porod, W., Hu, X.S.: ‘On-chip clocking for nanomagnet logic devices’, IEEE Trans. Nanotechnol., 2010, 9, pp. 348–351, (doi: 10.1109/TNANO.2010.2041248) (doi: 10.1109/TNANO.2010.2041248).
    43. 43)
      • 2. Liu, S., Hu, X.S., Nahas, J.J., Niemier, M.T., Porod, W., Bernstein, G.H.: ‘Magnetic-electrical interface for nanomagnet logic’, IEEE Trans. Nanotechnol., 2011, 10, pp. 757–763. (doi: 10.1109/TNANO.2010.2077645) (doi: 10.1109/TNANO.2010.2077645).
    44. 44)
      • 13. Huai, Y.: ‘Spin-transfer torque MRAM (STT-MRAM): challenges and prospects’, AAPPS Bull., 2008, 18, pp. 33–40.
    45. 45)
      • 7. Csaba, G., Porod, W., Csurgay, A.I.: ‘A computing architecture composed of field-coupled single domain nanomagnets clocked by magnetic field’, Int. J. Circ. Theory Appl., 2003, 31, pp. 67–82, (doi: 10.1002/cta.226) (doi: 10.1002/cta.226).
    46. 46)
      • 28. Hass, K.J., Donohoe, G.W., Hong, Y.K.: ‘SEU-resistant magnetic flip flops’. Proc. 12th NASA Symp. VLSI Design, 2005, pp. 1–8.
    47. 47)
      • 3. Orlov, A., Imre, A., Csaba, G., Ji, L., Porod, W., Bernstein, G.H.: ‘Magnetic quantum-dot cellular automata: recent developments and prospects’, J. Nanoelectron. Optoelectron., 2008, 3, pp. 1–14, (doi:10.1166/jno.2008.004) (doi: 10.1166/jno.2008.004).
    48. 48)
      • 1. Wilson, L.: ‘International technology roadmap for semiconductors: emerging research devices’ (2009en, 2009th edn.), Available at http://www.itrs.net.
    49. 49)
      • 19. Braganca, P.M., Katine, J.A., Emley, N.C., et al: ‘A three-terminal approach to developing spin-torque written magnetic random access memory cells’, IEEE Trans. Nanotechnol., 2009, 8, pp. 190–195, (doi: 10.1109/TNANO.2008.2005187) (doi: 10.1109/TNANO.2008.2005187).
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2013.0113
Loading

Related content

content/journals/10.1049/iet-cds.2013.0113
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading