access icon free 0.5-V bulk-driven CMOS operational amplifier

A new solution for a low-voltage bulk-driven CMOS operational amplifier is presented in this study. The amplifier is designed using 50 nm process parameters and optimised for 0.5 V supply voltage. The circuit consumes 100 μW, performing 74 dB open-loop gain, 59 nV/Hz1/2 input referred noise at 1 MHz and 4.8 MHz gain bandwidth product (GBP) for 20 pF load capacitance.

Inspec keywords: CMOS integrated circuits; low-power electronics; operational amplifiers

Other keywords: size 50 nm; voltage 0.5 V; noise performance; gain 74 dB; common-mode amplifiers; power 100 muW; low-voltage bulk-driven CMOS operational amplifier

Subjects: CMOS integrated circuits; Amplifiers

References

    1. 1)
      • 25. Huijsing, J.: ‘Multi-stage amplifier with capacitance nesting for frequency compensation’. US Patent Appl. Ser. 602234, filed 19 April 1984.
    2. 2)
      • 5. Grech, I., Micallef, J., Azzopardi, G., Debono, C.J.: ‘A low voltage wide-input-range bulk-input CMOS OTA’, Analog Integr. Circuits Signal Process., 2005, 43, (2), pp. 127136 (doi: 10.1007/s10470-005-6786-1).
    3. 3)
      • 14. Carrillo, J.M., Torelli, G., Pérez-Aloe, R., Valverde, J.M., Duque-Carrillo, J.F.: ‘Single pair bulk-driven CMOS input stage: a compact low-voltage analog cell for scaled technologies’, Integr. VLSI J., 2010, 43, (3), pp. 251257 (doi: 10.1016/j.vlsi.2010.03.002).
    4. 4)
      • 32. Baker, R.J.: ‘CMOS circuit design, layout and simulation’ (John Wiley & Sons, 2008, 2nd edn.).
    5. 5)
      • 23. Rosenfeld, J., Kozak, M., Friedman, E.G.: ‘A bulk-driven CMOS OTA with 68 dB gain’. Proc. IEEE Int. Conf. on Electron Circuits and Systems (ICECS), Vancouver, Canada, 2004, pp. 58.
    6. 6)
      • 2. Guziński, A., Białko, M., Matheau, J.C.: ‘Body-driven differential amplifier for applications in continuous-time active-C filter’. Proc. Europ. Conf. on Circuit Theory and Design, ECCTD, Paris, France, 1987, pp. 315320.
    7. 7)
      • 21. Haga, Y., Kale, I.: ‘Bulk-driven flipped voltage follower’. Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Taipei, Taiwan, 2009, pp. 27172720.
    8. 8)
      • 15. Carillo, J.M., Torelli, G., Duque-Carillo, J.F.: ‘Transconductance enhancement in bulk-driven input stages and its applications’, Analog Integr. Circuits Signal Process., 2011, 68, (2), pp. 207217 (doi: 10.1007/s10470-011-9603-z).
    9. 9)
      • 19. Aldokhaiel, A., Yamazaki, A., Ismail, M.: ‘A sub-1V CMOS bandgap voltage reference based on body-driven technique’. Proc. Northwest Workshop on Circuits and Systems, Montreal, Canada, 2004, pp. 58.
    10. 10)
      • 7. Chatterjee, S., Tsividis, Y., Kinget, P.: ‘0.5-V analog circuit techniques and their application in OTA and filter design’, IEEE J. Solid-State Circuits, 2005, 40, (12), pp. 23732387 (doi: 10.1109/JSSC.2005.856280).
    11. 11)
      • 33. Dhanasekaran, V., Silva-Martinez, J., Sánchez-Sinencio, E.: ‘Design of a three-stage class-AB 16 Ω headphone driver capable of handling wide range of load capacitance’, IEEE J. Solid-State Circuits, 2009, 44, (6), pp. 17341744 (doi: 10.1109/JSSC.2009.2020461).
    12. 12)
      • 6. Haga, Y., Zare-Hoseini, H., Berkovi, L., Kale, I.: ‘Design of a 0.8 V fully differential CMOS OTA using the bulk-driven technique’. Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Kobe, Japan, 2005, pp. 220223.
    13. 13)
      • 11. Trakimas, M., Sonkusale, S.: ‘A 0.5 V bulk-input OTA with improved common-mode feedback for low-frequency filtering applications’, Analog Integr. Circuits Signal Process., 2009, 59, pp. 8389 (doi: 10.1007/s10470-008-9236-z).
    14. 14)
      • 12. Monsurrò, P., Pennisi, S., Scotti, G., Trifiletti, A.: ‘0.9-V CMOS cascade amplifier with body-driven gain boosting’, Int. J. Circuit Theory Appl., 2009, 37, (2), pp. 193202 (doi: 10.1002/cta.539).
    15. 15)
      • 1. Yan, S., Sánchez-Sinencio, E.: ‘Low-voltage analog-circuit design techniques: a tutorial’, IEICE Trans. Analog Integr. Circuits Syst., 2000, E 00-A, (2), pp. 117.
    16. 16)
      • 13. Raikos, G., Vlassis, S.: ‘0.8 V bulk-driven operational amplifier’, Analog Integr. Circuits Signal Process., 2010, 63, (3), pp. 425432 (doi: 10.1007/s10470-009-9425-4).
    17. 17)
      • 22. Monsurrò, P., Pennisi, S., Scotti, G., Trifiletti, A.: ‘Exploiting the body of MOS devices for high performance analog design’, IEEE Circuits Syst. Mag., 2011, 11, (4), pp. 823 (doi: 10.1109/MCAS.2011.942751).
    18. 18)
      • 20. Haga, Y., Kale, I.: ‘CMOS buffer using complementary pair of bulk-driven super source followers’, Electron. Lett., 2009, 45, (18), pp. 917918 (doi: 10.1049/el.2009.1382).
    19. 19)
      • 17. Raikos, G., Vlassis, S.: ‘Low-voltage bulk-driven input stage with improved transconductance’, Int. J. Circuit Theory Appl., 2011, 39, (3), pp. 327339 (doi: 10.1002/cta.637).
    20. 20)
      • 8. Haga, Y., Morling, R.C.S., Kale, I.: ‘A new bulk-driven input stage design for sub 1-V CMOS op-amps’. Proc. IEEE Int. Symp. on Circuits and Systems (ISCAS), Island of Kos, Greece, 2006, pp. 15471550.
    21. 21)
      • 9. Carrillo, J.M., Torelli, G., Pérez-Aloe, R., Duque-Carrillo, J.F.: ‘1-V rail-to-rail CMOS op-amp with improved bulk-driven input stage’, IEEE J. Solid-State Circuits, 2007, 42, (3), pp. 508517 (doi: 10.1109/JSSC.2006.891717).
    22. 22)
      • 3. Blalock, B.J., Allen, P.E., Rincón-Mora, G.A.: ‘Designing 1-V op amps using standard digital CMOS technology’, IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., 1998, 45, (7), pp. 769780 (doi: 10.1109/82.700924).
    23. 23)
      • 29. Grasso, A.D., Palumbo, G., Pennisi, S.: ‘Analytical comparison of frequency compensation techniques in three-stage amplifiers’, Int. J. Circuit Theory Appl., 2008, 36, (1), pp. 5380 (doi: 10.1002/cta.397).
    24. 24)
      • 27. Huijsing, J.: ‘Operational amplifiers. Theory and design’ (Kluwer Academic Publishers, 2001).
    25. 25)
      • 24. Urban, Ch., Moon, J.E., Mukund, P.R.: ‘Scaling the bulk-driven MOSFET into deca-nanometer bulk CMOS processes’, Microelectron. Reliab., 2011, 51, (4), pp. 727732 (doi: 10.1016/j.microrel.2010.11.016).
    26. 26)
      • 4. Kulej, T.: ‘Low-voltage CMOS transconductance amplifier controlled from body terminals’, Bull. Pol. Acad. Sci., Tech. Sci., 1999, 47, (3), pp. 255261.
    27. 27)
      • 10. Fereira, L., Pimenta, T., Moreno, R.: ‘An ultra-low-voltage ultra-low-power CMOS Miller OTA with rail-to-rail input/output swing’, IEEE Trans. Circuits Syst. II, 2007, 54, (10), pp. 843847 (doi: 10.1109/TCSII.2007.902216).
    28. 28)
      • 30. Huang, W.J., Lu, S.H., Liu, S.I.: ‘Capacitor-free low-dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array’, IET Circuits Devices Syst., 2008, 2, (3), pp. 306316 (doi: 10.1049/iet-cds:20070343).
    29. 29)
      • 26. Eschauzier, R.G.H., Kerklaan, L.P.T., Huijsing, J.: ‘A 100 MHz 100 dB operational amplifier with multipath nested Miller compensation structure’, IEEE J. Solid-State Circuits, 1992, 27, (12), pp. 17091717 (doi: 10.1109/4.173096).
    30. 30)
      • 25. Huijsing, J.: ‘Multi-stage amplifier with capacitance nesting for frequency compensation’. US Patent Appl. Ser. 602234, filed 19April1984.
    31. 31)
      • 18. Zhang, X., El-Masry, E.I.: ‘A regulated body-driven CMOS current mirror for low voltage applications’, IEEE Trans. Circuits Syst. II, 2004, 51, (10), pp. 571577 (doi: 10.1109/TCSII.2004.834536).
    32. 32)
      • 16. Carrillo, J.M., Torelli, G., Dominguez, M.A., Duque-Carrillo, J.F.: ‘On the input common-mode voltage range of CMOS bulk-driven input stages’, Int. J. Circuit Theory Appl., 2011, 39, (6), pp. 649664 (doi: 10.1002/cta.667).
    33. 33)
      • 28. Cannizzaro, S., Grasso, A., Mita, R., Palumbo, G., Pennisi, S.: ‘Design procedures for three-stage CMOS OTAs with nested-Miller compensation’, IEEE Trans. Circuits Syst. I, 2007, 54, (5), pp. 933940 (doi: 10.1109/TCSI.2007.895520).
    34. 34)
      • 31. Marano, D., Palumbo, G., Pennisi, S.: ‘Step-response optimization techniques for low-power, high-load, three-stage operational amplifiers driving large capacitive loads’, IET Circuits Devices Syst., 2010, 4, (2), pp. 8798 (doi: 10.1049/iet-cds.2009.0126).
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