Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

access icon free Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits

  • Author(s): Xiaoming Chen 1 ; Hong Luo 1 ; Yu Wang 1 ; Yu Cao 2 ; Yuan Xie 3 ; Yuchun Ma 4 ; Huazhong Yang 1
    • View affiliations
    • Affiliations: 1: Department of Electronic Engineering, Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing 100084, People's Republic of China;
      2: Department of ECEE, Arizona State University, Tempe, Arizona 85287-5706, USA;
      3: Department of CSE, Pennsylvania State University, Pennsylvania 16802, USA;
      4: Department of Computer Science, Tsinghua National Laboratory for Information Science and Technology, Tsinghua University, Beijing 100084, People's Republic of China
  • Source: Volume 7, Issue 5, September 2013, p. 273 – 282
    DOI:  10.1049/iet-cds.2012.0361 , Print ISSN 1751-858X, Online ISSN 1751-8598
© The Institution of Engineering and Technology
Received 22/11/2012, Accepted 25/01/2013, Revised 23/01/2013, Published

Random telegraph noise (RTN) has become an important reliability issue in nanoscale circuits recently. This study proposes a simulation framework to evaluate the temporal performance of digital circuits under the impact of RTN at 16 nm technology node. Two fast algorithms with linear time complexity are proposed: statistical critical path analysis and normal distribution-based analysis. The simulation results reveal that the circuit delay degradation and variation induced by RTN are both >20% and the maximum degradation and variation can be >30%. The effect of power supply tuning and gate sizing techniques on mitigating RTN is also investigated.

Inspec keywords: power supply circuits; statistical analysis; digital circuits; circuit tuning; delay circuits; circuit noise; telegraphy; random noise; circuit reliability

Other keywords: performance degradation; circuit delay degradation; reliability; RTN; normal distribution-based analysis; statistical critical path analysis; gate sizing technique; random telegraph noise; temporal performance evaluation; nanoscale circuit; size 16 nm; digital circuit; power supply tuning effect; linear time complexity algorithm

Subjects: Digital electronics; Pulse circuits; Other topics in statistics; Reliability; Power electronics, supply and supervisory circuits

References

    1. 1)
      • 4. Luo, H., Wang, Y., Cao, Y., Xie, Y., Ma, Y., Yang, H.: ‘Temporal performance degradation under RTN: evaluation and mitigation for nanoscale circuits’. IEEE Computer Society Annual Symp. VLSI (ISVLSI), August 2012, pp. 183–188.
    2. 2)
      • 10. Campbell, J.P., Qin, J., Cheung, K.P., et al: ‘Random telegraph noise in highly scaled nMOSFETs’. IEEE Int. Reliability Physics Symp. (IRPS), April 2009, pp. 382–388.
    3. 3)
      • 2. Chen, X., Wang, Y., Cao, Y., Ma, Y., Yang, H.: ‘Variation-aware supply voltage assignment for simultaneous power and aging optimization’, IEEE Trans. Very Large Scale Integr. (VLSI) Syst., 2012, 20, (11), pp. 2143–2147 (doi: 10.1109/TVLSI.2011.2168433).
    4. 4)
      • 7. Campbell, J.P., Yu, L.C., Cheung, K.P., et al: ‘Large random telegraph noise in sub-threshold operation of nano-scale nMOSFETs’. IEEE Int. Conf. IC Design and Technology (ICICDT), May 2009, pp. 17–20.
    5. 5)
      • 9. Campbell, J.P., Qin, J., Cheung, K.P., et al: ‘The origins of random telegraph noise in highly scaled SiON nMOSFETs’. IEEE Int. Integrated Reliability Workshop (IRW), October 2008, pp. 1–16.
    6. 6)
      • 15. Aadithya, K.V., Demir, A., Venugopalan, S., Roychowdhury, J.: ‘SAMURAI: an accurate method for modelling and simulating non-stationary random telegraph noise in SRAMs’. Design, Automation Test in Europe Conf. Exhibition (DATE), March 2011, pp. 1–6.
    7. 7)
      • 6. Tega, N., Miki, H., Pagette, F., et al: ‘Increasing threshold voltage variation due to random telegraph noise in FETs as gate lengths scale to 20 nm’. Symp. VLSI Technology, June 2009, pp. 50–51.
    8. 8)
      • 1. Wang, Y., Luo, H., He, K., Luo, R., Yang, H., Xie, Y.: ‘Temperature-aware NBTI modeling and the impact of standby leakage reduction techniques on circuit performance degradation’, IEEE Trans. Dependable Secur. Comput., 2011, 8, (5), pp. 756–769 (doi: 10.1109/TDSC.2010.41).
    9. 9)
      • 8. Lee, A., Brown, A.R., Asenov, A., Roy, S.: ‘Random telegraph signal noise simulation of decanano MOSFETs subject to atomic scale structure variation’, Superlattices Microstruct., 2003, 34, (3–6), pp. 293–300 (doi: 10.1016/j.spmi.2004.03.027).
    10. 10)
      • 17. Leyris, C., Pilorget, S., Marin, M., Minondo, M., Jaouen, H.: ‘Random telegraph signal noise SPICE modeling for circuit simulators’. European Solid State Device Research Conf. (ESSDERC), September 2007, pp. 187–190.
    11. 11)
      • 23. Ghetti, A., Compagnoni, C.M., Biancardi, F., et al: ‘Scaling trends for random telegraph noise in deca-nanometer flash memories’. IEEE Int. Electron Devices Meeting (IEDM), December 2008, pp. 1–4.
    12. 12)
      • 22. Nagumo, T., Takeuchi, K., Hase, T., Hayashi, Y.: ‘Statistical characterization of trap position, energy, amplitude and time constants by RTN measurement of multiple individual traps’. IEEE Int. Electron Devices Meeting (IEDM), December 2010, pp. 28.3.1–28.3.4.
    13. 13)
      • 3. Luo, H., Chen, X., Velamala, J., et al: ‘Circuit-level delay modeling considering both TDDB and NBTI’. Int. Symp. Quality Electronic Design (ISQED), March 2011, pp. 1–8.
    14. 14)
      • 5. Tega, N., Miki, H., Ren, Z., et al: ‘Reduction of random telegraph noise in high-k/metal-gate stacks for 22 nm generation FETs’. IEEE Int. Electron Devices Meeting (IEDM), December 2009, pp. 1–4.
    15. 15)
      • 25. Billingsley, P.: ‘Probability and measure’ (Wiley Press, 1979, 2nd edn., 1986, 3rd edn., 1995).
    16. 16)
      • 11. Ghetti, A., Compagnoni, C.M., Spinelli, A.S., Visconti, A.: ‘Comprehensive analysis of random telegraph noise instability and its scaling in deca-nanometer flash memories’, IEEE Trans. Electron Devices, 2009, 56, (8), pp. 1746–1752 (doi: 10.1109/TED.2009.2024031).
    17. 17)
      • 12. Tega, N., Miki, H., Yamaoka, M., et al: ‘Impact of threshold voltage fluctuation due to random telegraph noise on scaled-down SRAM’. IEEE Int. Reliability Physics Symp. (IRPS), May 2008, pp. 541–546.
    18. 18)
      • 26. Clark, C.E.: ‘The greatest of a finite set of random variables’, Oper. Res., 1961, 9, (2), pp. 145–162 (doi: 10.1287/opre.9.2.145).
    19. 19)
      • 24. http://ptm.asu.edu/ (accessed November 2012).
    20. 20)
      • 16. Aadithya, K.V., Venogopalan, S., Demir, A., Roychowdhury, J.: ‘MUSTARD: a coupled, stochastic/deterministic, discrete/continuous technique for predicting the impact of random telegraph noise on SRAMs and DRAMs’. ACM/EDAC/IEEE Design Automation Conf. (DAC), June 2011, pp. 292–297.
    21. 21)
      • 13. Toh, S.O., Tsukamoto, Y., Guo, Z., Jones, L., Liu, T.K., Nikolic, B.: ‘Impact of random telegraph signals on Vmin in 45 nm SRAM’. IEEE Int. Electron Devices Meeting (IEDM), December 2009, pp. 1–4.
    22. 22)
      • 18. Tang, T.B., Murray, A.F.: ‘Integrating RTS noise into circuit analysis’. IEEE Int. Symp. Circuits and Systems (ISCAS), May 2009, pp. 585–588.
    23. 23)
      • 20. Ito, K., Matsumoto, T., Nishizawa, S., Sunagawa, H., Kobayashi, K., Onodera, H.: ‘Modeling of random telegraph noise under circuit operation – simulation and measurement of RTN-induced delay fluctuation’. Int. Symp. Quality Electronic Design (ISQED), March 2011, pp. 1–6.
    24. 24)
      • 14. Tanizawa, M., Ohbayashi, S., Okagaki, T., et al: ‘Application of a statistical compact model for random telegraph noise to scaled-SRAM Vmin analysis’. Symp. VLSI Technology (VLSIT), June 2010, pp. 95–96.
    25. 25)
      • 21. Lee, S., Cho, H.-J., Son, Y., Lee, D.S., Shin, H.: ‘Characterization of oxide traps leading to RTN in high-k and metal gate MOSFETs’. IEEE Int. Electron Devices Meeting (IEDM), December 2009, pp. 1–4.
    26. 26)
      • 19. Ye, Y., Wang, C.-C., Cao, Y.: ‘Simulation of random telegraph noise with 2-stage equivalent circuit’. IEEE/ACM Int. Conf. Computer-Aided Design (ICCAD), November 2010, pp. 709–713.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2012.0361
Loading

Related content

content/journals/10.1049/iet-cds.2012.0361
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
Print this page
This is a required field
Please enter a valid email address