Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution

Access Full Text

Statistical estimation of leakage power dissipation in nano-scale complementary metal oxide semiconductor digital circuits using generalised extreme value distribution

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

In this study, the authors present an accurate approach for the estimation of statistical distribution of leakage power consumption in the presence of process variations in nano-scale complementary metal oxide semiconductor (CMOS) technologies. The technique, which is additive with respect to the individual gate leakage values, employs a generalised extreme value (GEV) distribution. Compared with the previous methods based on (two-parameter) lognormal distribution, this method uses the GEV distribution with three parameters to increase the accuracy. Using the suggested distribution, the leakage yield of the circuits may be modelled. The accuracy of the approach is studied by comparing its results with those of a previous technique and HSPICE-based Monte Carlo simulations on ISCAS85 benchmark circuits for 45 nm CMOS technology. The comparison reveals a higher accuracy for the proposed approach. The proposed distribution does not add to the complexity and cost of simulations compared with the case of the lognormal distribution based on the additive approach.

Inspec keywords: Monte Carlo methods; statistical distributions; CMOS digital integrated circuits

Other keywords: individual gate leakage values; nanoscale complementary metal oxide semiconductor digital circuits; statistical distribution estimation; nanoscale CMOS technologies; leakage power dissipation; HSPICE-based Monte Carlo simulations; ISCAS85 benchmark circuits; size 45 nm; leakage power consumption; GEV distribution; lognormal distribution; generalised extreme value distribution

Subjects: Monte Carlo methods; CMOS integrated circuits; Other topics in statistics

References

    1. 1)
    2. 2)
      • Nassif, S.R.: `Modeling and analysis of manufacturing variations', Proc. IEEE Custom Integrated Circuits Conf., 2001, p. 223–228.
    3. 3)
      • http://www.eda.ncsu.edu/wiki/FreePDK45:Contents, accessed September 2011.
    4. 4)
    5. 5)
      • Rao, R., Devgan, A., Blaauw, D., Sylvester, D.: `Parametric yield estimation considering leakage variability', Proc. DAC, June 2004, p. 442–447.
    6. 6)
      • Li, T., Yu, Z.: `Statistical analysis of full-chip leakage power considering junction tunneling leakage', Proc. DAC, June 2007, p. 99–102.
    7. 7)
      • G. Muraleedharan , C. Guedes , C. Lucas . (2011) Characteristic and moment generating functions of generalized extreme value distribution (GEV), sea level rise, coastal engineering, shorelines and tides.
    8. 8)
      • Wang, J.M., Srinivas, B., Ma, D., Chen, C.C.P., Li, J.: `System-level power and thermal modeling by orthogonal polynomial based response surface approach (OPRS)', Proc. ICCAD, 2005, p. 728–735.
    9. 9)
    10. 10)
      • Rao, R., Devgan, A., Blaauw, D., Sylvester, D.: `Parametric yield estimation considering leakage variability', Proc. Design Automation Conf., 2004, p. 442–447.
    11. 11)
      • Borkar, S., Karnik, T., Narendra, S., Tschanz, J., Keshavarzi, A., De, V.: `Parameter variation and impact on circuits and microarchitecture', Proc. Design Automation Conf., 2003, p. 338–342.
    12. 12)
    13. 13)
    14. 14)
      • Chang, H., Sapatnekar, S.S.: `Full-chip analysis of leakage power under process variations, including spatial correlations', Proc. DAC, June 2005, p. 523–528.
    15. 15)
      • Li, X., Le, J., Pileggi, L.: `Projection based statistical analysis of full-chip leakage power with non-log-normal distributions', Proc. DAC, June 2006, p. 103–108.
    16. 16)
      • Brglez, F., Fujiwara, H.: `A Neutral netlist of 10 combinational benchmark circuits', Proc. IEEE Int. Symp. on Circuits and Systems, 1985, Piscataway, NJ, p. 695–698.
    17. 17)
      • Bhardwaj, S., Vrudhula, S.: `Leakage minimization of nano-scale circuits in the presence of systematic and random variations', Proc. DAC, 2005, p. 541–546.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2011.0348
Loading

Related content

content/journals/10.1049/iet-cds.2011.0348
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading