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This study presents a subthreshold complementary metal oxide semiconductor (CMOS) voltage reference circuit that adopts dynamical body bias to compensate the process-related reference voltage fluctuation. The proposed circuit generates a mean reference voltage of 0.781 V at 1.2 V supply and 27°C, reduces the standard deviation (σ) of the reference voltage from 11 mV to only 3 mV, and meanwhile improves the power supply rejection ratio from −30.7 to −51.4 dB. The average temperature coefficient measured from 0 to 100°C is 48 ppm/°C, and the line regulation is 0.34%/V in a supply voltage ranging from 1.2 to 2.3 V. The maximum supply current is 8.1 µA at 1.2 V supply and 100°C, and the chip area is 0.0533 mm2 in 0.13-µm CMOS technology.
References
-
-
1)
-
K. Ueno ,
T. Hirose ,
T. Asai ,
Y. Amemiya
.
A 300 nW, 15 ppm/°C, 20 ppm/V CMOS voltage reference circuit consisting of subthreshold MOSFETs.
IEEE J. Solid-State Circuits
,
7 ,
2047 -
2054
-
2)
-
Naro, G.D., Lombardo, G., Paolino, C., Lullo, G.: `A low-power fully-MOSFET voltage reference generator for 90 nm CMOS technology', ICICDT 2006, May 2006.
-
3)
-
H. Banba
.
A CMOS bandgap reference circuit with sub-1-V operation.
IEEE J. Solid-State Circuits
,
670 -
673
-
4)
-
H. Luo
.
Bulk-compensated technique and its application to subthreshold ICs.
Electron. Lett.
,
16 ,
1105 -
1106
-
5)
-
M.H. Cheng ,
Z.W. Wu
.
Low-power low-voltage reference using peaking current mirror circuit.
Electron. Lett.
,
10 ,
572 -
573
-
6)
-
M.A. Duarte-Villaseñor ,
E. Tlelo-Cuautle ,
L. Gerardo de la Fraga
.
Binary genetic encoding for the synthesis of mixed-mode circuit topologies.
Circuits, Syst. Signal Process.
,
3 ,
849 -
863
-
7)
-
Y.-B. Gu ,
S.-F. Yueh ,
T.-W. Chang ,
K.-C. Huang
.
CMOS voltage reference with multiple outputs.
IET Circuits Devices Syst.
,
2 ,
222 -
226
-
8)
-
K.N. Leung ,
P.K.T. Mok
.
A sub-1-V 15 ppm/°C CMOS bandgap voltage reference without requiring low threshold voltage device.
IEEE J. Solid-State Circuits
,
4 ,
526 -
530
-
9)
-
L. Magnelli ,
F. Crupi ,
P. Corsonello ,
C. Pace ,
G. Iannaccone
.
A 2.6 nW, 0.45 V temperature-compensated subthreshold CMOS voltage reference.
IEEE J. Solid-State Circuits
,
2 ,
465 -
474
-
10)
-
A. Becker-Gomez ,
T.L. Viswanathan ,
T.R. Viswanathan
.
A low-supply-voltage CMOS sub-bandgap reference.
IEEE Trans. Circuits Syst. II, Exp. Briefs
,
7 ,
609 -
613
-
11)
-
P. Huang ,
H. Lin ,
Y. Lin
.
A simple subthreshold CMOS voltage reference circuit with channel-length modulation compensation.
IEEE Trans. Circuits Syst. II, Exp. Briefs
,
9 ,
882 -
885
-
12)
-
G. De Vita ,
G. Iannaccone
.
A sub-1-V, 10 ppm/°C, nanopower voltage reference generator.
IEEE J. Solid-State Circuits
,
7 ,
1536 -
1542
-
13)
-
Narendra, S., Haycock, M., Govindarajulu, V., Erraguntla, V.: `1.1 V 1 GHz cmmunications router with on-chip body bias in 150 nm CMOS', ISSCC, 2002.
-
14)
-
K.N. Leung
.
A CMOS voltage reference based on weighted difference of gate-source voltages between PMOS and NMOS transistors for low drop out regulators.
IEEE J. Solid-State Circuits
,
1 ,
146 -
150
-
15)
-
F. Serra-Graells ,
J.L. Huertas
.
Sub-1V CMOS proportional-to-absolute-temperature references.
IEEE J. Solid State Circuits
,
1 ,
84 -
88
-
16)
-
G. Giustolisi
.
A low-voltage low-power voltage reference based on subthreshold MOSFETs.
IEEE J. Solid-State Circuits
,
1 ,
151 -
154
-
17)
-
X. Xia ,
L. Xie ,
W. Sun ,
L. Shi
.
Temperature-stable voltage reference based on different threshold voltages of NMOS transistors.
IET Circuits Devices Syst.
,
5 ,
233 -
238
-
18)
-
He, J., Chen, D., Geiger, R.: `Systematic characterization of subthreshold-MOSFETs-based voltage references for ultra low power low voltage applications', Proc. MWSCAS 2010, August 2010, p. 280–283.
-
19)
-
Lin, H., Chang, D.: `A low-voltage process corner insensitive subthreshold CMOS voltage reference circuit', Proc. ICICDT 2006, May 2006.
-
20)
-
X. Ming ,
Y. Ma ,
Z. Zhou ,
B. Zhang
.
A high-precision compensated CMOS bandgap voltage reference without resistors.
IEEE Trans. Circuits Syst. II, Exp. Briefs
,
10 ,
767 -
771
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