Technique for the reduction of output voltage ripple of switched capacitor-based DC–DC converters

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© The Institution of Engineering and Technology
Published 30/07/2012

Abstract

Switch capacitor DC–DC converter is an emerging concept for high dropout application. This paper discusses techniques for output voltage ripple reduction of an embedded dual-switch capacitor – linear regulator-based hybrid DC–DC converter. In spite of deploying the advantage of PSRR property of the linear regulator, the ripple at the output of the convertor is still high. To alleviate this, a new technique of further reduction of the output ripple by introducing synthesised counter ripples through the linear regulator is presented. The conventional and new technique of ripple reduction has been analysed with the help of small signal equivalent circuits. These techniques have been implemented with a hybrid converter for 3.3 V-to-1.35 V conversions. A test chip is fabricated in a 0.18-µm standard digital CMOS process to demonstrate the efficacy of the proposed technique. It is found that the trend of ripple reduction by ripple synthesiser in measured results is consistent with the simulation results and also observed in the measured results that the ripple synthesiser reduces the output ripple of a hybrid converter by the factor of 0.52 and 0.45 for the load current of 2.2 mA and 7.3 mA, respectively.

Inspec keywords: DC-DC power convertors; CMOS digital integrated circuits; capacitors; equivalent circuits

Other keywords: digital CMOS process; linear regulator-based hybrid DC-DC converter; ripple synthesiser; voltage 3.3 V to 1.35 V; output voltage ripple reduction; current 2.2 mA to 7.3 mA; embedded dual-switch capacitor; signal equivalent circuits; ripple reduction; size 0.18 mum; switched capacitor-based DC-DC converters; linear regulator

Subjects: Capacitors; Digital electronics; Power electronics, supply and supervisory circuits; CMOS integrated circuits

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