© The Institution of Engineering and Technology
Novel high-performance ternary circuits for nanotechnology are presented here. Each of these carbon nanotube field-effect transistor (CNFET)-based circuits implements all the possible kinds of ternary logic, including negative, positive and standard ternary logics, in one structure. The proposed designs have good driving capability and large noise margins and are robust. These circuits are designed based on the unique properties of CNFETs, such as the capability of setting the desired threshold voltage by changing the diameters of the nanotubes. This property of CNFETs makes them very suitable for the multiple-Vt design method. The proposed circuits are simulated exhaustively, using Synopsys HSPICE with 32 nm-CNFET technology in various test situations and different supply voltages. Simulation results demonstrate great improvements in terms of speed, power consumption and insusceptibility to process variations with respect to other conventional and state-of-the-art 32 nm complementary metal-oxide semiconductor and CNFET-based ternary circuits. For instance at 0.9 V, the proposed ternary logic and arithmetic circuits consume on average 53 and 40% less energy, respectively, compared to the CNFET-based ternary logic and arithmetic circuits, recently proposed in the literature.
References
-
-
1)
-
S.L. Hurst
.
Multiple-valued logic its status and its future.
IEEE Trans. Comput.
,
1160 -
1179
-
2)
-
J. Deng ,
H.-S.P. Wong
.
A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application – Part II: full device model and circuit performance benchmarking.
IEEE Trans. Electron Device
,
12 ,
3195 -
3205
-
3)
-
Dhande, A.P., Ingole, V.T.: `Design and implementation of 2-bit ternary ALU slice', Proc. Int. Conf. on IEEE – Science of Electronics, Technology of Information and Telecommunication, March 2005, Sousse, Tunisia, p. 17–21.
-
4)
-
Gundersen, H., Berg, Y.: `Fast addition using balanced ternary counters designed with CMOS semi-floating gate devices', Proc. Int. Symp. on Multiple-Valued Logic, May 2007, Oslo, Norway, p. 30.
-
5)
-
Mouftah, H.T., Jordan, I.B.: `Integrated circuits for ternary logic', Proc. Int. Symp. on Multiple Valued Logic, May 1974, Morgantown, West Virginia, United States, p. 285–302.
-
6)
-
P. Keshavarzian ,
K. Navi
.
Efficient carbon nanotube galois field circuit design.
IEICE Electron. Express
,
9 ,
546 -
552
-
7)
-
D. Mateo ,
A. Rubio
.
Quasi-adiabatic ternary CMOS logic.
Electron. Lett.
,
2 ,
99 -
101
-
8)
-
Bok, K.Y., Kim, Y.B., Lombardi, F.: `Novel design methodology to optimize the speed and power of the CNTFET circuits', Proc. IEEE Int. Midwest Symp. on Circuits and Systems, August 2009, Cancun, Mexico, p. 1130–1133.
-
9)
-
Berg, Y., Aunet, S., Mirmotahari, O., Høvin, M.: `Novel recharge semi-floating-gate CMOS logic for multiple-valued systems', Proc. IEEE Int. Symp. on Circuits and Systems, May 2003, Bangkok, Thailand, 5, p. V-193–V-196.
-
10)
-
K. Roy ,
S. Mukhopadhyay ,
H. Mahmoodi-Meimand
.
Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits.
Proc. IEEE
,
2 ,
305 -
327
-
11)
-
A. Shoarinejad ,
S.A. Ung ,
W. Badawy
.
Low power single bit full adder cells.
Canadian J. Electr. Comput. Eng.
,
1 ,
3 -
9
-
12)
-
A. Srivastava ,
K. Venkatapathy
.
Design and implementation of a low power ternary full adder.
VLSI Des.
,
1 ,
75 -
81
-
13)
-
K.C. Smith
.
A multiple valued logic: a tutorial and appreciation.
Computer
,
4 ,
17 -
27
-
14)
-
S. Lin ,
Y.-B. Kim ,
F. Lombardi
.
CNTFET-based design of ternary logic gates and arithmetic circuits.
IEEE Trans. Nanotechnol.
,
2 ,
217 -
225
-
15)
-
A. Srivastava
.
Back gate bias method of threshold voltage control for the design of low voltage CMOS ternary logic circuits.
Microelectron. Reliab.
,
12 ,
2107 -
2110
-
16)
-
Berg, Y., Næss, Ø., Aunet, S., Lomsdalen, I., Høvin, M.: `A novel floating-gate binary signal to multiple-valued signal converter for multiple-valued CMOS logic', Proc. IEEE Int. Conf. on Electronics, Circuits and Systems, September 2002, Dubrovnik, Croatia, 2, p. 579–582.
-
17)
-
K. Navi ,
M.H. Moaiyeri ,
R. Faghih Mirzaee ,
O. Hashemipour ,
B. Mazloom Nezhad
.
Two new low-power full adders based on majority-not gates.
Microelectron. J.
,
1 ,
126 -
130
-
18)
-
Dubrova, E.: `Multiple-valued logic in VLSI: challenges and opportunities', Proc. NORCHIP Conf., November 1999, Oslo, Norway, p. 340–350.
-
19)
-
M.H. Moaiyeri ,
R. Faghih Mirzaee ,
K. Navi ,
T. Nikoubin ,
O. Kavehei
.
Novel direct designs for 3-input XOR function for low-power and high-speed applications.
Int. J. Electron.
,
6 ,
647 -
662
-
20)
-
Shahidipour, H., Ahmadi, A., Maharatna, K.: `Effect of variability in SWCNT-based logic gates', Proc. Int. Symp. on Integrated Circuits, December 2009, Singapore, p. 252–255.
-
21)
-
M.H. Moaiyer ,
R. Faghih Mirzaee ,
K. Navi ,
O. Hashemipour
.
Efficient CNTFET-based ternary full adder cells for nanoelectronics.
Nano-Micro Letters
,
1 ,
43 -
50
-
22)
-
A. Raychowdhury ,
K. Roy
.
Carbon-nanotube-based voltage-mode multiple-valued logic design.
IEEE Trans. Nanotechnol.
,
168 -
179
-
23)
-
K. El Shabrawy ,
K. Maharatna ,
D. Bagnall ,
B.M. Al-Hashimi
.
Modeling SWCNT bandgap and effective mass variation using a Monte Carlo approach.
IEEE Trans. Nanotechnol.
,
2 ,
184 -
193
-
24)
-
A. Hueng ,
H.T. Mouftah
.
Depletion/enhancement CMOS for a low power family of three-valued logic circuits.
IEEE J. Solid-State Circuits
,
2 ,
609 -
616
-
25)
-
F. Toto ,
R. Saletti
.
CMOS dynamic ternary circuit with full logic swing and zero-static power consumption.
Electron. Lett.
,
11 ,
1083 -
1084
-
26)
-
K. Navi ,
M. Rashtian ,
A. Khatir ,
P. Keshavarzian ,
O. Hashemipour
.
High speed capacitor-inverter based carbon nanotube full adder.
Nanoscale Res. Lett.
,
5 ,
859 -
862
-
27)
-
Lin, S., Kim, Y., Lombardi, F.: `A novel CNFET based ternary logic gate design', Proc. IEEE Int. Midwest Symp. on Circuits and Systems, August 2009, Cancun, Mexico, p. 435–438.
-
28)
-
J. Deng ,
H.S.P. Wong
.
A compact SPICE model for carbon-nanotube field-effect transistors including nonidealities and its application – Part I: model of the intrinsic channel region.
IEEE Trans. Electron Devices
,
12 ,
1198 -
1202
-
29)
-
H.T. Mouftah ,
K.C. Smith
.
Injected voltage low-power CMOS for 3-valued logic.
IEE Proc. G
,
6 ,
270 -
272
-
30)
-
Cho, G., Kim, Y., Lombardi, F.: `Performance evaluation of CNFET-based logic gates', Proc. IEEE Int. Instrumentation and Measurement Technology Conf., May 2009, Singapore, p. 909–912.
-
31)
-
A. Raychowdhury ,
K. Roy
.
Carbon nanotube electronics: design of high-performance and low-power digital circuits.
IEEE Trans. Circuits Syst.
,
11 ,
2391 -
2401
-
32)
-
A.K. Abu El-Seoud ,
M. El-Banna ,
M.A. Hakim
.
On modelling and characterization of single electron transistor.
Int. J. Electron.
,
6 ,
573 -
585
-
33)
-
K. Navi ,
S. Sayedsalehi ,
R. Farazkish ,
M. Rahimi Azghadi
.
Five-input majority gate, a new device for quantum-dot cellular automata.
J. Comput. Theor. Nanosci.
,
8 ,
1546 -
1553
-
34)
-
P. Keshavarzian ,
K. Navi
.
Universal ternary logic circuit design through carbon nanotube technology.
Int. J. Nanotechnol.
,
942 -
953
-
35)
-
S. Goel ,
A. Kumar ,
M.A. Bayoumi
.
Design of robust, energy-efficient full adders for deep-submicrometer design using hybrid-CMOS logic style.
IEEE Trans. Very Large Scale Integr. Syst.
,
12 ,
1309 -
1321
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