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A zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter (ADC) using an offset compensation method is presented. The ADC has been fabricated by 0.18 µm CMOS process with a die area of 0.69 mm2. While the common-mode voltage tracking circuit is turned on, for an input signal of 41 MHz with the sampling rate of 100 MS/s, the measured SNDR is 43.82 dB with effective number of bits 7.0-bit, the DNL ±0.79-LSB and the INL ±1.24-LSB. The power is 8 mW at a supply voltage of 1.8 V.
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http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2010.0329
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