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Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensation

Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensation

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A zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter (ADC) using an offset compensation method is presented. The ADC has been fabricated by 0.18 µm CMOS process with a die area of 0.69 mm2. While the common-mode voltage tracking circuit is turned on, for an input signal of 41 MHz with the sampling rate of 100 MS/s, the measured SNDR is 43.82 dB with effective number of bits 7.0-bit, the DNL ±0.79-LSB and the INL ±1.24-LSB. The power is 8 mW at a supply voltage of 1.8 V.

References

    1. 1)
    2. 2)
      • Yoo, S.M., Oh, T.H., Lee, H.Y., Moon, K.H., Kim, J.W.: `A 3.0 V 12b 120 MSample/s CMOS pipelined ADC', Proc. IEEE Int. Symp. on Circuits and Systems, 2006, p. 1023–1026.
    3. 3)
      • S. Limotyrakis , S.D. Kulchycki , D. Su , B.A. Wooley . A 150 MS/s 8b 71 mW time-interleaved ADC in 0.18 µm CMOS. IEEE J. Solid-State Circuits , 5 , 1057 - 1067
    4. 4)
      • Choi, H.C., Kim, Y.J., Lee, S.W.: `A 52 mW 0.56 mm', Proc. IEEE Int. Symp. on Circuits and Systems, 2008, p. 9–12.
    5. 5)
    6. 6)
      • Brooks, L., Lee, H.S.: `A 12b 50 MS/s fully differential zero-crossing-based ADC without CMFB', ISSCC, 2009, p. 166–167.
    7. 7)
    8. 8)
      • Lee, H.Y., Liu, S.I.: `A 8-bit 140 MS/s pipelined adc using folded sample-and-hold stage', Electron Devices and Solid-State Circuits Conf., December 2007, p. 357–360.
    9. 9)
      • Oh, T.H., Lee, H.Y., Kim, J.H.: `A 16b 10 MS/s digitally self-calibrated ADC with time constant control', Proc. IEEE Custom Integrated Circuits Integrated Conf., 2008, p. 113–116.
    10. 10)
      • H.Y. Lee , S.I. Liu . A 10-bit 140 MS/s pipelined ADC using folded sample-and hold stage. IEEE Int. Symp. on Circuits and Systems , 976 - 979
    11. 11)
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