Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensation

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Zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter with offset compensation

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Published

A zero-crossing-based 8-bit 100 MS/s pipelined analogue-to-digital converter (ADC) using an offset compensation method is presented. The ADC has been fabricated by 0.18 µm CMOS process with a die area of 0.69 mm2. While the common-mode voltage tracking circuit is turned on, for an input signal of 41 MHz with the sampling rate of 100 MS/s, the measured SNDR is 43.82 dB with effective number of bits 7.0-bit, the DNL ±0.79-LSB and the INL ±1.24-LSB. The power is 8 mW at a supply voltage of 1.8 V.

Inspec keywords: analogue-digital conversion; CMOS digital integrated circuits

Other keywords: frequency 41 MHz; offset compensation method; bit rate 100 Mbit/s; power 8 mW; word length 7.0 bit; zero-crossing-based pipelined analogue-to-digital converter; SNDR; ADC; CMOS process; size 0.18 mum; voltage 1.8 V; common-mode voltage tracking circuit

Subjects: CMOS integrated circuits; A/D and D/A convertors; A/D and D/A convertors

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