Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s

Author(s): C. Desmouliers ; E. Oruklu ; J. Saniie
DOI: 10.1049/iet-cds.2010.0259

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Author(s): C. Desmouliers ¹ ; E. Oruklu ¹ ; J. Saniie ¹
- Affiliations: 1: Department of Electrical and Computer Engineering, Illinois Institute of Technology, Chicago, USA
Source: Volume 5, Issue 4, July 2011, p. 321 – 328
DOI: 10.1049/iet-cds.2010.0259 , Print ISSN 1751-858X, Online ISSN 1751-8598

Designing a universal embedded hardware architecture for discrete wavelet transform is a challenging problem because of the diversity among wavelet kernel filters. In this work, the authors present three different hardware architectures for implementing multiple wavelet kernels. The first scheme utilises fixed, parallel hardware for all the required wavelet kernels, whereas the second scheme employs a processing element (PE)-based datapath that can be configured for multiple wavelet filters during run-time. The third scheme makes use of partial run-time configuration of FPGA units for dynamically programming any desired wavelet filter. As a case study, the authors present FPGA synthesis results for simultaneous implementation of six different wavelets for the proposed methods. Performance analysis and comparison of area, timing and power results are presented for the Virtex-II Pro FPGA implementations.

References

1. 1)
  - Daubechies, I., Swelden, W.: `Factoring wavelet transforms into lifting steps', Technical report, Bell Laboratories, 1996.
2. 2)
  - T. Acharya , C. Chakrabarti . A survey on lifting-based discrete wavelet transform architectures. J. VLSI Signal Process. , 3 , 321 - 339
3. 3)
  - H. Liao , M.K. Mandal , B.F. Cockburn . Efficient architectures for 1-D and 2-Dlifting-based wavelet transform. IEEE Trans. Signal Process. , 5 , 1315 - 1326
4. 4)
  - HWICAP: Xilinx product specification, available at: http://www.xilinx.com/support/documentation/ip_documentation/opb_hwicp.pdf.
5. 5)
  - S. Masud , J. McCanny . Reusable silicon IP cores for discrete wavelet transform applications. IEEE Trans. Circuits Syst. I, Fundam. Theory Appl. , 6 , 1114 - 1124
6. 6)
  - JPEG2000 Committee Drafts. Available at http://www.jpeg.org/public/fcd15444-1.pdf.
7. 7)
  - K. Andra , C. Chakrabarti , T. Acharya . A VLSI architecture for lifting-based forward and inverse wavelet transform. IEEE Trans. Signal Process. , 4 , 966 - 977
8. 8)
  - S. Lee , S. Lim . VLSI design of a wavelet processing core. IEEE Trans. Circuits Syst. Video Technol. , 11 , 1350 - 1361
9. 9)
  - FSL, (Fast Simplex Link) bus: Xilinx application note, available at http://www.xilinx.com/support/documentation/ip_documentation/fs_v20.pdf.
10. 10)
  - French, M., Anderson, E., Kang, D.: `Autonomous system on chip adaptation through partial runtime reconfiguration', Proc. IEEE Symp. on Field-Programmable Custom Computing Machines, 2008, p. 77–86.
11. 11)
  - C.-T. Huang , P.-C. Tseng , L.-G. Chen . Flipping structure: an efficient VLSI architecture for lifting-based discrete wavelet transform. IEEE Trans. Signal Process. , 1080 - 1089
12. 12)
  - E. Oruklu , J. Saniie . Dynamically reconfigurable architecture design for ultrasonic imaging. IEEE Trans. Instrum. Meas. , 8 , 2856 - 2866
13. 13)
  - Fernandez, G., Periaswamy, P., Sweldens, W.: `LIFTPACK: a software package for wavelet transforms using lifting', Proc. SPIE, Wavelet Applications Signal Image Processing IV, 1996, 2825, p. 396–408.
14. 14)
  - Oruklu, E., Saniie, J.: `Ultrasonic flaw detection using discrete wavelet transform for NDE applications', IEEE Ultrasonics Symp., 2004, 2, p. 1054–1057.
15. 15)
  - B.-F. Wu , C.-F. Lin . A high-performance and memory-efficient pipeline architecture for the 5/3 and 9/7 discrete wavelet transform of JPEG2000 codec. IEEE Trans. Circuits Syst. Video Technol. , 12 , 1615 - 1627
16. 16)
  - Liu, C.C., Shiau, Y.H., Jou, J.M.: `Design and implementation of a progressive image coding chip based on the lifted wavelet transform', Proc. 11th VLSI Design/CAD Symp., 2000, p. 49–52.
17. 17)
  - Xpower: Xilinx product, available at: http://www.xilinx.com/products/design_tools/logic_design/verification/xpower.htm.
18. 18)
  - Lian, C.J., Chen, K.F., Chen, H.H., Chen, L.G.: `Lifting based discrete wavelet transform architecture for JPEG2000', IEEE Int. Symp. on Circuits and Systems, 2001, p. 445–448.
19. 19)
  - C. Huang , P. Tseng , L. Chen . Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method. Proc. IEEE Int. Symp. on Circuits Systems, (ISCAS) , 565 - 568
20. 20)
  - K.A. Kotteri , A.E. Bell , J.E. Carletta . Design of multiplierless, high-performance, wavelet filter banks with image compression applications. IEEE Trans. Circuits Syst. – I: Regular Papers , 3 , 483 - 494
21. 21)
  - Sweldens, W.: `The lifting scheme: A new philosophy in biorthogonal wavelet constructions', Proc. SPIE, Wavelet Applications in Signal and Image Processing III, 1995, 2569, p. 68–79.
22. 22)
  - Raaijmakers, S., Wong, S.: `Run-time partial re-configuration for removal, placement and routing on the Virtex-II Pro', Proc. Int. Conf. on Field Programmable Logic and Applications, (FPL 2007), 2007, p. 679–683.
23. 23)
  - Tseng, P., Huang, C., Chen, L.: `Reconfigurable discrete wavelet transform architecture for advanced multimedia systems', Proc. IEEE Workshop on Signal Process Systems (SIPS), 2003, p. 137–141.
24. 24)
  - H. Liao , M.K. Mandal , B.F. Cockburn . Efficient implementation of the lifting-based discrete wavelet transform. Electron. Lett. , 18 , 1010 - 1012
25. 25)
  - B. Blodget , C. Bobda , M. Huebner , A. Niyonkuru . (2004) Partial and dynamically reconfiguration of Xilinx Virtex-II FPGAs, Field programmable logic and applications.
26. 26)
  - Reichel, J.: `On the arithmetic and bandwidth complexity of the lifting scheme', Proc. Int. Conf. on Image Processing, 2001, 3, p. 198–201.
27. 27)
  - S. Craven , P. Athanas . Dynamic hardware development. Int. J. Reconfigurable Comput.
28. 28)
  - Zhang, X., Rabah, H., Weber, S.: `Cluster-based hybrid reconfigurable architecture for auto-adaptive SoC', Proc. 14th IEEE Int. Conf. on Electronics, Circuits and Systems, ICECS, 2007, p. 979–982.

Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s

Discrete wavelet transform realisation using run-time reconfiguration of field programmable gate array (FPGA)s

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