© The Institution of Engineering and Technology
A sense amplifier detects a small signal and amplifies it to produce a large signal. However, a sensing failure may occur owing to the offset voltage caused by the mismatch of paired transistors in the sense amplifier. Since the yield of a sense amplifier is the strong function of the offset voltage, estimation of the offset voltage and its statistical distribution is critical in designing sense amplifiers. As offset voltage can be assumed to follow a Gaussian distribution, its standard deviation (1-sigma, σOS) can be estimated from a simple variance model for paired transistors. However, owing to secondary effects such as differential charge injection, drain-induced barrier lowering and stack effect, σOS estimated using the variance model deviates from that obtained from statistical (Monte-Carlo) simulation, and the deviation becomes larger as technology scales down. This study analyses secondary effects on the offset voltage in the most commonly used latch-type sense amplifiers and suggests novel σOS estimation model. The proposed model, which considers secondary effects, can accurately estimate σOS even when technology scales down. This study also presents the trend of the influence of secondary effects on the offset voltage with technology scaling.
References
-
-
1)
-
M.J. Pelgrom ,
A.C. Duinmaijer ,
A.P.G. Welbers
.
Matching properties of MOS transistors.
IEEE J. Solid-State Circuit
,
1433 -
1440
-
2)
-
K. Bernstein ,
D.J. Frank ,
A.E. Gattiker
.
High-performance CMOS variability in the 65-nm regime and beyond.
IBM J. Res. Dev.
,
433 -
449
-
3)
-
Iniguez, B., Lazaro, A., Hamid, H.A.E.: `Charge-based compact modeling of multiple-gate MOSFET', IEEE 2007 Custom Integrated Circuits Conf., 2007, p. 49–56.
-
4)
-
http://www.eas.asu.deu/~ptm/.
-
5)
-
Quenette, V., Lemoigne, P., Rideau, D.: `Electical characterization and compact modeling of MOSFET body effect', Int. Conf. on Ultimate Integration of Silicon, March 2008, Udine, Italy, p. 163–166.
-
6)
-
A.J. Bhavnagarwala ,
X. Tang ,
J.D. Meindl
.
The impact of intrinsic device fluctuation on CMOS SRAM cell stability.
IEEE J. Solid-State Circuits
,
4 ,
658 -
665
-
7)
-
B. Wicht ,
T. Nirschl ,
D. Schmitt-Landsiedel
.
Yield and speed optimization of a latch-type voltage sense amplifier.
IEEE J. Solid-State Circuits
,
7 ,
1148 -
1158
-
8)
-
Nassif, S.R.: `Modeling and analysis of manufacturing variations', IEEE Custom Integrated Circuit Conf., May 2001, San Diego, USA, p. 223–228.
-
9)
-
R. Singh ,
N. Bhat
.
An offset compensation technique for latch type sense amplifier in high-speed low-power SRAMs.
IEEE Trans. VLSI Syst.
,
6 ,
652 -
657
-
10)
-
Tsiatouhas, Y., Chrisanthopoulus, A., Kamoulakos, A.G., Haniotais, T.: `New memory sense amplifier design in CMOS technology', IEEE Int. Conf. on Electronics, Circuits and Systems, December 2000, Jounieh, Lebanon, p. 19–22.
-
11)
-
Putra, A., Tsunomura, T., Nishida, A., Kamohara, S., Takeuchi, K., Hiramoto, T.: `Impact of fixed charge at MOSFETs’ SiO2/Si interface on Vth variation', Int. Conf. on Simulation of Semiconductor Processes and Devices, 2008, p. 25–28.
-
12)
-
S. Mukhopadhyay ,
H. Mahmoodi ,
K. Roy
.
Modeling of failure probability and statistical design of SRAM array for yield enhancement in nanoscaled CMOS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.
,
12 ,
1859 -
1880
-
13)
-
D. Bol ,
R. Ambroise ,
D. Flandre ,
J.-D. Legat
.
Interests and limitations of technology scaling for subthreshold logic.
IEEE Trans. VLSI Syst.
,
1 ,
1508 -
1519
-
14)
-
A. Asenov ,
S. Kaya ,
J.H. Davies
.
Intrinsic threshold voltage fluctuations in decanano MOSFETs due tolocal oxide thickness variations.
IEEE Trans. Electron Devices
,
1 ,
112 -
119
-
15)
-
R.R. Troutman
.
VLSI limitations from drain-induced barrier lowering.
IEEE Trans. Electron Devices
,
4 ,
461 -
469
-
16)
-
M.J. Kumar ,
M. Siva
.
The ground plane in buried oxide for controlling short-channel effects in nanoscale SOI MOSFETs.
IEEE Trans. Electron Devices
,
6 ,
1554 -
1557
-
17)
-
S. Saha
.
Scaling considerations for high performance 25 nm Metal-oxide-semiconductor field effect transistors.
J. Vac. Sci. Technol. B, Microelectron. Nanometer Struct.
,
6 ,
2240 -
2246
-
18)
-
Reid, D., Millar, C., Roy, G., Roy, S., Asenov, A.: `Understanding LER-induced statistical variability: a 35,000 sample 3D simulation study', European Solid-State Device Research Conf., 2009, p. 423–426.
-
19)
-
Meterelliyoz, M., Song, P., Stellari, F., Kulkarni, J.P., Roy, K.: `A high sensitivity process variation sensor utilizing sub-threshold operation', Custom Integrated Circuits Conf., 2008, p. 125–128.
-
20)
-
K. Agarwal ,
N. Nassif
.
The impact of random device variation on SRAM cell stability in sub-90 nm CMOS technologies.
IEEE Trans. VLSI Syst.
,
1 ,
86 -
97
-
21)
-
T. Mizuno ,
J. Okamura ,
A. Toriumi
.
Experimental study of threshold voltage fluctuation due to statistical variation of channel dopant number in MOSFETs.
IEEE Trans. Electron Devices
,
11 ,
2216 -
2221
-
22)
-
S. Saha
.
Design considerations for 25 nm MOSFET devices.
Solid-State Electron.
,
10 ,
1851 -
1857
-
23)
-
X. Tang ,
V. De ,
J.D. Meindl
.
Intrinsic MOSFET parameter fluctuations due to random dopant placement.
IEEE Trans. VLSI Syst.
,
4 ,
369 -
376
-
24)
-
H. Nho ,
S.-S. Yoon ,
S. Wong ,
S.O. Jung
.
Statistical simulation methodology for sub-100 nm memory design.
Electron. Lett.
,
16 ,
869 -
870
-
25)
-
H. Nho ,
S.-S. Yoon ,
S. Wong ,
S.O. Jung
.
Numerical estimation of yield in sub-100 nm SRAM design using MC simulation.
IEEE Trans. Circuits Syst. II
,
9 ,
907 -
911
-
26)
-
P.A. Stolk ,
F.P. Widdershoven ,
D.B.M. Klassen
.
Modeling statistical dopant fluctuations in MOS transistors.
IEEE Trans. Electron. Devices
,
9 ,
1960 -
1971
-
27)
-
Yu, S., Zhao, Y., Song, Y., Du, G., Kang, J., Han, R., Liu, X.: `3-D simulation of geometrical variations impact on nanoscale FinFETs', Int. Conf. on Solid-State and Integrated-Circuit Technology, 2008, p. 408–411.
-
28)
-
A. Raychowndhury ,
B.C. Paul ,
K. Roy
.
Computing with subthreshold leakage: device/circuit/architecture co-design for ultralow-power subthreshold operation.
IEEE Trans. VLSI Syst.
,
11 ,
1213 -
1224
-
29)
-
B.H. Calhoun ,
A. Wang ,
A. Chandrakasan
.
Modeling and sizing for minimum energy operation in subthreshold circuits.
IEEE J. Solid-State Circuits
,
9 ,
1778 -
1786
-
30)
-
R. Vaddi ,
S. Dasgupta ,
P.A. Agarwal
.
Device and circuit co-design robustness studies in the subtreshold logic for ultralow-power application for 32 nm CMOS.
IEEE Trans. Electron Devices
,
3 ,
654 -
664
-
31)
-
Khun, K.J.: `Reducing variation in advanced logic technologies: approaches to process and design manufacturability of nanoscale CMOS', IEEE Int. Electron Devices Meeting, December 2007, Washington, DC, USA, p. 471–474.
-
32)
-
Yeung, J., Mahmoodi, H.: `Robust sense amplifier design under random dopant fluctuations in nano-scale CMOS technologies', IEEE Int. SOC Conf., September 2006, p. 261–264.
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2010.0092
Related content
content/journals/10.1049/iet-cds.2010.0092
pub_keyword,iet_inspecKeyword,pub_concept
6
6