5 GHz low power frequency synthesiser with dual-modulus counter

Access Full Text

5 GHz low power frequency synthesiser with dual-modulus counter

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

A 5 GHz low power frequency synthesiser with a dual-modulus counter (DMC) was fabricated in 0.18 µm CMOS technology. The DMC allows to reduce the power consumption and to provide the functionality of the divider without a swallower counter. The settling time takes no more than 5 µs with an adaptive bandwidth topology. The measured phase noise is −87 dBc/Hz and −119 dBc/Hz at 10 kHz and 1 MHz offset frequencies, respectively. The reference spurs level is lower than −55 dBc at 10 MHz offset. The proposed synthesiser covers frequencies between 5.14 and 5.86 GHz in steps of 20 MHz and consumes 16.4 mW at 1.5 V supply voltage.

Inspec keywords: frequency synthesizers; CMOS integrated circuits; low-power electronics; frequency dividers

Other keywords: low power frequency synthesiser; adaptive bandwidth topology; size 0.18 mum; frequency 5.14 GHz to 5.86 GHz; dual-modulus counter; voltage 1.5 V; frequency 5 GHz; power 16.4 mW; CMOS technology

Subjects: Convertors; Signal generators; CMOS integrated circuits

References

    1. 1)
      • T.K.K. Kan , G.C.T. Leung , H.C. Luong . A 2V 1.8 GHz fully integrated CMOS dual-loop frequency synthesizer. IEEE J. Solid-State Circuits , 8 , 1012 - 1020
    2. 2)
      • Kim, H.S., El-Gamal, M.N.: `A 1-V fully integrated CMOS frequency synthesizer for 5-GHz WLAN', Proc. IEEE Int. Circuits Systems, May 2005, p. 4389–4392.
    3. 3)
      • S. Levantino , C. Samori , A. Bonfanti . Frequency dependence on bais current in 5-GHz CMOS VCOs: impact on tuning range and flicker noise upconversion. IEEE J. Solid-State Circuits , 8 , 1003 - 1011
    4. 4)
      • C.S. Vaucher , I. Ferencic , M. Locher , S. Sedvallson , U. Voegeli , Z. Wang . A family of low-power truly modular programmable dividers in standard 0.35-µm CMOS technology. IEEE J. Solid-State Circuits , 7 , 1039 - 1045
    5. 5)
      • J.M.C. Wong , V.S.L. Cheung , H.C. Luong . A 1-V 2.5-mW 5.2-GHz frequency divider in a 0.35-µm CMOS process. IEEE J. Solid-State Circuits , 10 , 1643 - 1648
    6. 6)
      • Chiu, W.H., Chan, T.S., Lin, T.H.: `A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-µm', Proc. IEEE Asian Solid-State Circuits, November 2007, p. 456–459.
    7. 7)
      • M. Mansuri , D. Liu , C.K.K. Yang . Fast frequency acquisition phase-frequency detectors for Gsamples/s phase-locked loops. IEEE J. Solid-State Circuits , 10 , 1331 - 1334
    8. 8)
      • N.H. Fong , J.O. Plouchart , N. Zamdmer . Design of wide-band CMOS VCO for multiband wireless LAN applications. IEEE J. Solid-State Circuits , 8 , 1333 - 1342
    9. 9)
      • J. Craninckx , M.S.J. Steyaert . A 1.75-GHz/3-V dual-modulus divide-by-128/129 prescaler in 0.7-µm CMOS. IEEE J. Solid-State Circuits , 7 , 890 - 897
    10. 10)
      • X.P. Yu , M.A. Do , J.G. Ma , K.S. Yeo , R. Wu , G.Q. Yan . Low power high-speed CMOS dual-modulus prescaler design with imbalanced phase-switching technique. IEE Proc. Circuits Devices Syst. , 2 , 127 - 132
    11. 11)
      • C.Y. Yang , S.I. Liu . Fast-switching frequency with a discriminator-aided phase detector. IEEE J. Solid-State Circuits , 10 , 780 - 787
    12. 12)
      • H.H. Chang , J.C. Wu . A 723-MHz 17.2 mW CMOS programmable counter. IEEE J. Solid-State Circuits , 10 , 1572 - 1575
    13. 13)
      • N. Krishnapura , P.R. Kinget . A 5.3-GHz programmable divider for HiPerLAN in 0.25-µm CMOS. IEEE J. Solid-State Circuits , 7 , 1019 - 1024
    14. 14)
      • S.H. Lee , H.J. Park . A CMOS high-speed wide-range programmable counter. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. , 9 , 638 - 642
    15. 15)
      • P.Y. Deng , J.F. Kiang . A 5-GHz CMOS frequency synthesizer with an injection-locked frequency divider and differential switched capacitors. IEEE Trans. Circuits Syst. I , 2 , 320 - 326
    16. 16)
      • Houlgate, M.P., Olszewski, D.J., Abdelhalim, K., MacEachern, L.: `Adaptable MOS current mode logic for use in a multi-band RF prescaler', Proc. Int. Symp. Circuits and Systems, May 2004, 4, p. 329–332.
    17. 17)
      • J.W.M. Rogers , J.A. Macedo , C. Plett . The effect of caractor nonlinearity on the phase noise of completely integrated VCOs. IEEE J. Solid-State Circuits , 9 , 1360 - 1367
    18. 18)
      • C.Y. Kuo , J.Y. Chang , S.I. Liu . A spur-reduction technique for a 5-GHz frequency synthesizer. IEEE Trans. Circuits Syst. I , 3 , 526 - 533
    19. 19)
      • X.P. Yu , M.A. Do , L. Jia , J.G. Ma , K.S. Yeo . Design of a low power wide-band high resolution programmable frequency divider. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. , 1098 - 1103
    20. 20)
      • Kim, T., Lee, S., Choi, G., Kim, S., Kim, T.: `Swallow counterless DMP PLL', Proc. 6th Int. Conf. VLSI and CAD, October 1999, p. 606–608.
    21. 21)
      • K.H. Cheng , W.B. Yang , C.M. Ying . A dual-slope phase frequency detector and charge-pump architecture to achieve fast locking of phase-locked loop. IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process. , 11 , 892 - 896
    22. 22)
      • H.R. Rategh , H. Samavati , T.H. Lee . A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver. IEEE J. Solid-State Circuits , 5 , 780 - 787
    23. 23)
      • E. Tournier , M. Sie , J. Graffeuil . High-speed dual-modulus prescaler architecture for programmable digital frequency dividers. Electron. Lett. , 24 , 1433 - 1434
    24. 24)
      • H.O. Johansson . A simple precharged CMOS phase frequency detector. IEEE J. Solid-State Circuits , 2 , 295 - 299
    25. 25)
      • A.D. Berry , A.M. Niknejad , R. Meyer . A 1.8-GHz LC VCO with 1.3-GHz tuning range and digital amplitude calibration. IEEE J. Solid-State Circuits , 4 , 909 - 917
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2009.0118
Loading

Related content

content/journals/10.1049/iet-cds.2009.0118
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading