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Impact of finite impulse response digital-to-analogue converter delay on the stability of continuous-time sigma-delta modulators with pulse-with modulation in the feedback path

Impact of finite impulse response digital-to-analogue converter delay on the stability of continuous-time sigma-delta modulators with pulse-with modulation in the feedback path

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Published

A finite impulse response (FIR) digital-to-analogue converter (DAC) in the feedback path has been shown to reduce the sensitivity to clock jitter of continuous-time sigma-delta modulators (SDMs). A method to analyse the impact of the additional loop delay introduced by the FIR-DAC on the modulator stability is proposed in this paper. This method is applied to the pulse width modulated (PWM) SDM. As in the PWM-SDM the pulse-width modulator is sampled at a frequency higher than the quantiser, a discrete time model is first obtained which operates with only one clock. The stability analysis is based on a linear model with a new criterion which takes into account the quantiser overloading. The theoretical results are in accordance with the results obtained by simulation. Here, it is shown that PWM-SDMs with an order greater than 2 can be designed maintaining the low sensitivity of multiple feedback architectures to a delay in the outer loop.

Inspec keywords: circuit feedback; pulse width modulation; continuous time filters; sigma-delta modulation; FIR filters

Other keywords: continuous-time sigma-delta modulators; pulse-width modulation; quantiser overloading; stability analysis; discrete time model; finite impulse response digital-to-analogue converter; feedback path; loop delay

Subjects: Digital filters; A/D and D/A convertors; Digital filters; A/D and D/A convertors

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