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In the nanoscale CMOS process, the problem of leakage current causes the performance of the analog circuits to degrade. The leakage current of a loop filter, which is realised by MOS capacitors, significantly degrades the jitter performance of a phase-locked loop. A leakage suppression circuit is presented by using a combination of switchable varactors and current sources to compensate the leakage of MOS capacitors in a loop filter. This PLL has been fabricated in a 65 nm CMOS process and the core area is 0.4×0.5 mm2. With the leakage suppression circuit, the peak-to-peak jitter and the rms jitter are 43 and 5.36 ps, respectively. The power is 17 mW for a 1.2 V supply.
Inspec keywords: UHF integrated circuits; jitter; phase locked loops; leakage currents; CMOS analogue integrated circuits; UHF filters; varactors; MOS capacitors
Other keywords:
Subjects: Modulators, demodulators, discriminators and mixers; Microwave integrated circuits; CMOS integrated circuits; Filters and other networks; Capacitors