Switched positive/negative charge pump design using standard CMOS transistors

Access Full Text

Switched positive/negative charge pump design using standard CMOS transistors

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© The Institution of Engineering and Technology
Published

The most common approach used in the generation of on-chip high voltages are based on Dickson's charge pump. In embedded and stand-alone designs of non-volatile memories, multiple charge pumps are utilised to generate both positive and negative voltages. Owing to high voltage drop across their terminals, high-voltage transistors are used to implement charge transfer function in many charge pump designs. The authors present a switchable charge pump design that utilises standard (low voltage) transistors to generate positive or negative high voltage based on the required mode of operation. Such design eliminates the need for multiple charge pumps, hence resulting in better utilisation of the available silicon area. Moreover, the use of standard transistors is shown to provide better performance/efficiency than designs that uses high-voltage transistors.

Inspec keywords: transfer functions; integrated circuit design; flash memories; charge pump circuits; CMOS integrated circuits

Other keywords: CMOS transistors; Dickson charge pump; charge transfer function; switched polarity charge pump design; high-voltage transistors

Subjects: Semiconductor storage; Memory circuits; Semiconductor integrated circuit design, layout, modelling and testing; Digital circuit design, modelling and testing; CMOS integrated circuits; Power electronics, supply and supervisory circuits

References

    1. 1)
      • Richelli, A., Mensi, L., Colalongo, L., Rolandi, P.L., Kovacs-Vanjna, Z.M.: `A 1.2 V-to-8 V charge pump with improved power efficiency for non-volatile memories', IEEE Int. Solid-State Circuits Conf., February 2007, San Francisco, California, p. 522–523.
    2. 2)
      • T. Tanazawa , T. Tanaka , K. Takeuchi , H. Nakamura . Circuit techniques for a 1.8-V-only NAND flash memory. IEEE J. Solid-State Circuits , 1 , 84 - 89
    3. 3)
      • Hong, D., El-Gamal, M.: `Low operating voltage and short settling time CMOS charge pump for MEMS application', Proc. 2003 Int. Symp. on Circuits and Systems, May 2003, Bangkok, Thailand, p. 281–284.
    4. 4)
      • http://www.mosis.com/, accessed April 2009.
    5. 5)
      • R. Pelliconi , D. Iezzi , A. Baroni , M. Pasotti , P.L. Rolandi . Power efficient charge pump in deep submicron standard CMOS technology. IEEE J. Solid-State Circuits , 6 , 1068 - 1071
    6. 6)
      • A. Cabrini , L. Gobbi , G. Torelli . Enhanced charge pump for ultra-low-voltage applications. Electron. Lett. , 9 , 512 - 514
    7. 7)
      • J.F. Dickson . On-chip high-voltage generation in NMOS integrated circuits using improved voltage multiplier technique. IEEE J. Solid-State Circuits , 3 , 374 - 378
    8. 8)
      • N. Yan , H. Min . High efficiency all-PMOS charge pump for low voltage operations. Electron. Lett. , 5 , 277 - 279
    9. 9)
      • G. Palumbo , D. Pappalardo , M. Gaibotti . Charge pump circuits: power consumption optimization – a summary. IEEE Trans. Circuits Syst. I: Fundam. Theory Appl. , 11 , 1535 - 1542
    10. 10)
      • P. Favrat , P. Deval , M. Declercq . A high-efficiency CMOS voltage doubler. IEEE J. Solid-State Circuits , 3 , 410 - 416
    11. 11)
      • T. Tanazawa , T. Tanaka . A dynamic analysis of the Dickson charge pump circuit. IEEE J. Solid-State Circuits , 8 , 1231 - 1240
    12. 12)
      • Favrat, P., Declercq, M.: `A new CMOS on-chip high-voltage generator', Proc. 24th European Solid-State Circuit Conf., September 1998, Hague, The Netherlands, p. 104–107.
    13. 13)
      • Khouri, O., Gregori, S., Cabrini, A., Micheloni, R., Torelli, G.: `Improved charge pump for flash memory applications in triple-well CMOS technology', Proc. 2002 Int. Symp. on Circuits and Systems, May 2002, Scottsdale, Arizona, p. 1322–1326.
    14. 14)
      • S. Atsumi , A. Umezawa , T. Tanzawa . A channel-erasing 1.8-V-only 32-Mb NOR flash EEPROM with a bitline direct sensing scheme. IEEE J. Solid-State Circuits , 11 , 1648 - 1654
    15. 15)
      • A. Umezawa , S. Atsumi , M. Kuriyama . A 5V-only operation 0.6μm flash EEPROM with row decoder scheme in triple-well structure. IEEE J. Solid-State Circuits , 11 , 1540 - 1546
    16. 16)
      • J. Wu , K. Chang . MOS charge pumps for low-voltage operation. IEEE J. Solid-State Circuits , 4 , 592 - 597
http://iet.metastore.ingenta.com/content/journals/10.1049/iet-cds.2008.0349
Loading

Related content

content/journals/10.1049/iet-cds.2008.0349
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading