A novel flash fast-locking digital phase-locked loop: design and simulations

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A novel flash fast-locking digital phase-locked loop: design and simulations

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Published

A flash digital phase-locked loop (DPLL) is designed using 0.18 µm CMOS process and a 3.3 V power supply. It operates in the frequency range 200 MHz–2 GHz. The DPLL operation includes two stages: (i) a novel coarse-tuning stage based on a flash algorithm similar to the algorithm employed in flash A/D converters, and (ii) a fine-tuning stage similar to conventional DPLLs. The flash portion of the DPLL is made up of frequency comparators, an encoder and a decoder which drives a multiple charge pump (CP)/lowpass filter (LPF) combination. Design considerations of the flash DPLL circuit components as well as implementation using Cadence design tools are presented. Spectre simulations were also performed and demonstrated a significant improvement in the lock time of the flash DPLL as compared to the conventional DPLL. By increasing the number of frequency comparators, the lock time is expected to be always less than 100 ns in the above-mentioned frequency range.

Inspec keywords: charge pump circuits; comparators (circuits); CMOS digital integrated circuits; digital phase locked loops; low-pass filters

Other keywords: Spectre simulations; flash fast-locking digital phase-locked loop; frequency comparators; flash algorithm; CMOS process; coarse-tuning stage; size 0.18 mum; Cadence design tools; charge pump-lowpass filter combination; frequency 200 MHz to 2 GHz; voltage 3.3 V; DPLL design; fine-tuning stage

Subjects: Other digital circuits; Modulators, demodulators, discriminators and mixers; CMOS integrated circuits

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