Scalable and bijective cells for C-testable iterative logic array architectures

Author(s): B.-Y. Ye ; P.-Y. Yeh ; S.-Y. Kuo ; I.-Y. Chen
DOI: 10.1049/iet-cds.2008.0296

For access to this article, please select a purchase option:

Buy article PDF

Buy Knowledge Pack

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership

Recommend Title Publication to library

IET Circuits, Devices & Systems — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

Author(s): B.-Y. Ye ¹ ; P.-Y. Yeh ² ; S.-Y. Kuo ^{1, 2, 3} ; I.-Y. Chen ⁴
- Affiliations: 1: Graduate Institute of Electronics Engineering, BL-522, National Taiwan University, Taipei, Taiwan
  2: Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan
  3: Department of Electrical Engineering, National Taiwan University of Science and Technology, Taipei, Taiwan
  4: Department of Electrical Engineering, National Taipei University of Technology, Taipei, Taiwan
Source: Volume 3, Issue 4, August 2009, p. 172 – 181
DOI: 10.1049/iet-cds.2008.0296 , Print ISSN 1751-858X, Online ISSN 1751-8598

In this study, a novel idea is proposed to test arithmetic circuits with both acceptable number of test patterns (NTP) and hardware overhead (HO). First, highly scalable full adder and full substractor are proposed. A scalable cell consists of n bit-level cells and has both hardware and bijective scalability. These simple scalable cells establish the relationship between the NTP and the HO, which is a function of n. By adjusting the value of n, we can obtain an optimal balance between HO and NTP. An iterative logic array (ILA) based on these scalable cells will still be C-testable. Based on the novel bijective and scalable cells, the authors propose C-testable designs for multiplier-accumulator (MAC), N-tap finite impulse response (FIR) filter and matrix multiplication, where the (HO, NTP) pairs with n=2 are only about (4.87%, 74). For 4×4 matrix multiplication, the total test time of the proposed method is only about 0.19% of that with the scan-chain method. With scalable and bijective cells, all the proposed ILA solutions can be connected together into a bigger non-homogeneous ILA and save lots of test pins and build-in self-test (BIST) area. In addition, the proposed scalable cells induce a simple and systematic way to have balanced results. The proposed technique makes the ILA-based DFT schemes more practical, systematic and useful for real-world complex applications.

References

1. 1)
  - Kautz, W.H.: `Testing for faults in combinational cellular logic arrays', Proc. Eighth Annual Symp. Switching, Automata Theory, 1967, p. 161–174.
2. 2)
  - Smith, G.L.: `Model for delay faults based upon path', Proc. IEEE Int. Test Conf., 1985, p. 342–349.
3. 3)
  - T. Sridhar , J.P. Hayes . Design of easily testable bit-sliced systems. IEEE Trans. Comput. , 11 , 842 - 854
4. 4)
  - P.R. Menon , A.D. Friedman . Fault detection in iterative arrays. IEEE Trans. Comput. , 524 - 535
5. 5)
  - Y. Zorian . (2000) Principles of testing electronic systems.
6. 6)
  - H. Fujiwara , S. Toida . The complexity of fault detection problems for combinational logic circuits. IEEE Trans. Comput. , 6 , 555 - 560
7. 7)
  - S.K. Lu , C.W. Wu , S.-Y. Kuo . Enhancing testability of VLSI arrays for fast Fourier transform. IEE Proc. E , 3 , 161 - 166
8. 8)
  - J. Shen , F. Ferguson . The design of easily testable VLSI array multipliers. IEEE Trans. Comput. , 6 , 554 - 560
9. 9)
  - H. Rahaman , J. Mathew , D.K. Pradhan . C-testable bit parallel multipliers over GF(2(m)). ACM Trans. Des. Autom. Electron. Syst. , 5
10. 10)
  - Aziz, S.M.: `C-testable modified Booth's array multiplier', Proc. Eighth Int. Conf. VLSI Design, 1995, 4–7, p. 278–282.
11. 11)
  - A.D. Friedman . Easily testable iterative systems. IEEE Trans. Comput. , 1061 - 1064
12. 12)
  - C.Y. Su , C.W. Wu . Testing iterative logic arrays for sequential faults with a constant number of patterns. IEEE Trans. Comput. , 4 , 495 - 501
13. 13)
  - D. Gizopoulos , A. Paschalis , D. Nikolos , C. Halatsis . Linear-testable and C-testable Nx×Ny modified Booth multipliers. IEE Proc. Comput. Digit. Tech. , 1 , 44 - 48
14. 14)
  - M. Psarakis , D. Gizopoulos , A. Paschalis . Built-in sequential fault self-testing of array multipliers. IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst. , 3 , 449 - 460
15. 15)
  - F. Lombardi . On a new class of C-testable systolic arrays. Integration , 269 - 283
16. 16)
  - C.W. Wu , P.R. Cappello . Easily testable iterative logic arrays. IEEE Trans. Comput. , 6 , 640 - 652
17. 17)
  - S.-K. Lu , C.-W. Wu , R.-Z. Hwang . Cell delay fault testing for iterative logic arrays. J. Electron. Testing: Theory Appl. , 3 , 311 - 316
18. 18)
  - Cheng, W.T., Patel, J.H.: `Testing in two-dimensional iterative logic arrays', Proc. Int. Symp. Fault Tolerant Computing, 1986, p. 76–81.
19. 19)
  - M. Psarakis , D. Gizopoulos , A. Paschalis , Y. Zorian . Sequential fault modeling and test pattern generation for CMOS iterative logic arrays. IEEE Trans. Comput. , 10 , 1083 - 1098
20. 20)
  - Rahaman, H., Mathew, J., Pradhan, D.K.: `Constant function independent test set for fault detection in bit parallel multipliers in GF(2', 20thConf. VLSI Design, January 2007, p. 479–484.
21. 21)
  - Pramanick, A.K., Reddy, S.M.: `On detection of delay faults', Proc. IEEE Int. Test Conf., 1988, p. 845–856.
22. 22)
  - W.A.J. Waller , S.M. Aziz . C-testable parallel multiplier using differential cascade voltage switch (DCVS) logic. IFIP Trans. A , 133 - 142
23. 23)
  - W.K. Huang , F. Lombardi . On an improved design approach for C-testable orthogonal iterative arrays. IEEE Trans. Comput.-Aided Des. Circuits Syst. , 5 , 609 - 615
24. 24)
  - H.C. Liang , P.H. Huang , Y.F. Tang . Testing transition delay faults in modified booth multipliers. IEEE Trans. Comput.-Aided Des. Circuits Syst. , 9 , 1693 - 1697
25. 25)
  - C.E. Stroud . (2002) A designer's guide to built-in self-test.
26. 26)
  - D. Gizopoulos , A. Paschalis , Y. Zorian . Effective built-in self-test for booth multipliers. IEEE Des. Test Comput. , 105 - 111
27. 27)
  - H. Elhuni , A. Vergis , L. Kinney . C-testability of two-dimensional iterative arrays. IEEE Trans. Comput.-Aided Des. Circuits Syst. , 4 , 573 - 581
28. 28)
  - S.-K. Lu , M.-J. Lu . Enhancing delay fault testability for FIR filters based on realistic sequential cell fault model. DELTA 2004 , 416 - 418
29. 29)
  - E.M. Aboulhamid , E. Cerny . Built-in testing of one-dimensional unilateral iterative arrays. IEEE Trans. Comput. , 6 , 560 - 564
30. 30)
  - S.K. Lu , J.C. Wang , C.W. Wu . C-testable design techniques for iterative logic arrays. IEEE Trans. VLSI , 1 , 146 - 152
31. 31)
  - N. Jha , S. Gupta . (2003) Testing of digital systems.
32. 32)
  - J. Galiay , Y. Crouzet , M. Vergiault . Physical versus logical fault models in MOS LSI circuits, impact on their testability. IEEE Trans. Comput. , 6 , 527 - 531
33. 33)
  - R. Parthasarathy , S.M. Reddy . A testable design of iterative logic arrays. IEEE Trans. Comput. , 11 , 833 - 841
34. 34)
  - S.K. Lu . Delay fault testing for CMOS iterative logic arrays with a constant number of patterns. IEICE Trans. Inf. Syst. , 12 , 2659 - 2665
35. 35)
  - A. Vergis , K. Steiglitz . Testability conditions for bilateral arrays of combinational cells. IEEE Trans. Comput. , 1 , 13 - 26

Scalable and bijective cells for C-testable iterative logic array architectures

Scalable and bijective cells for C-testable iterative logic array architectures

Buy article PDF

Buy Knowledge Pack

Thank you

References

Related content