Temperature-stable voltage reference based on different threshold voltages of NMOS transistors

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Temperature-stable voltage reference based on different threshold voltages of NMOS transistors

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A temperature-stable voltage reference based on threshold voltages of enhancement and depletion NMOS transistors has been presented and implemented with a 0.5 µm DPDM CMOS technology. The problem of a fixed voltage reference value is avoided by different parameter design. A significant reduce of temperature dependence of mobility is also achieved. The chip's area is 0.014 mm2. The test results show that the operation supply voltage is from 2 to 5 V, the maximum supply current is 8.24 µA, and the average reference voltage is 765 mV with an average line regulation of ±0.187%/V. A typical temperature coefficient of 39.2 ppm/°C for a temperature range of 0–100°C is obtained. The power-supply rejection ratio, without any filtering capacitors, is −46 dB at 100 Hz and −32 dB at 1 MHz for the smallest supply voltage.

Inspec keywords: CMOS integrated circuits; MOSFET; reference circuits

Other keywords: current 8.24 muA; temperature-stable voltage reference-based threshold voltage; temperature 0 degC to 100 degC; temperature coefficient; DPDM CMOS technology; voltage 2 V to 5 V; power-supply rejection ratio; voltage 765 mV; NMOS transistor; size 0.5 mum

Subjects: Insulated gate field effect transistors; CMOS integrated circuits

References

    1. 1)
      • G. De Vita , G. Iannaccone . A sub-1 V, 10 ppm/°C, nanopower voltage reference generator. IEEE J. Solid-State Circuits , 1536 - 1542
    2. 2)
      • K. Sanborn , M. Dongsheng , V. Ivanov . A sub-1-V low-noise bandgap voltage reference. IEEE J. Solid-State Circuits , 2466 - 2481
    3. 3)
    4. 4)
    5. 5)
      • Harrison, W.T., Connelly, J.A., Stair, R.: `An improved current-mode CMOS voltage reference', Proc. 2001 Southwest Symp., SSMSD, 2001, p. 23–27.
    6. 6)
    7. 7)
    8. 8)
      • Hu, Y., Hu, G., Zhu, D., Xu, Y., Yu, J.: `Design on micro power dissipation E/D NMOS reference source', 2007 International Symposium on Microwave, Antenna, Propagation and EMC Technologies for Wireless Communications, 16–17 August 2007, p. 1408–1411.
    9. 9)
      • H. Tanaka , Y. Nakagome , J. Etoh , E. Yamasaki , M. Aoki , K. Miyazawa . Sub-1-µA dynamic reference voltage generator for battery-operated DRAMs. IEEE J. Solid-State Circuits , 448 - 453
    10. 10)
      • R.T. Perry , S.H. Lewis , A.P. Brokaw , T.R. Viswanathan . A 1.4 V supply CMOS fractional bandgap reference. IEEE J. Solid-State Circuits , 2180 - 2186
    11. 11)
      • R.A. Blauschild , P.A. Tucci , R.S. Muller , R.G. Meyer . A new NMOS temperature-stable voltage reference. IEEE J. Solid-State Circuits , 767 - 774
    12. 12)
      • Strik, S.: `Bandgap voltage reference: errors and techniques for their minimization', Baltic Electronics Conference, 2006 International, October 2006, p. 1–4.
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