Transient analysis of bang–bang phase locked loops

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Transient analysis of bang–bang phase locked loops

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This work gives insight into the behaviour of second-order bang–bang phase locked loops in the far from lock region. This region, while largely unexplored, is of particular interest as PLL behaviour in this region determines locking time and capture range. By analysing PLL cycle slipping behaviour in this region, the transient response for the system is derived. Expressions for first-order system stability and locking time are also presented.

Inspec keywords: transient analysis; phase locked loops

Other keywords: bang-bang phase locked loops; locking time; transient analysis; first-order system stability

Subjects: General circuit analysis and synthesis methods; Modulators, demodulators, discriminators and mixers

References

    1. 1)
      • J. Lee , K.S. Kundert , B. Razavi . Analysis and modeling of bang–bang clock and data recovery circuits. IEEE J. Solid State Circuits , 1571 - 1580
    2. 2)
      • Ramezani, M., Salama, C.A.T.: `Jitter analysis of a PLL-based CDR with a bang–bang phase detector', Circuits and Systems, 45th Midwest Symposium on, 2002, 3, p. III393–III396.
    3. 3)
      • M. Chan , A. Postula , Y. Ding . A bang–bang PLL employing dynamic gain control for low jitter and fast lock times. Analog Integr. Circuits Signal Process. , 131 - 140
    4. 4)
      • Vichienchom, K., Liu, W.: `Analysis of phase noise due to bang–bang phase detector in PLL-based clock and data recovery circuits', Circuits and Systems, 2003 International Symposium on, 2003, 1, p. I617–I620.
    5. 5)
      • N. DaDalt . (2005) A design-oriented study of the nonlinear dynamics of digital bang–bang PLLs.
    6. 6)
      • Chan, M., Postula, A., Ding, Y.: `PLLSim – an ultra fast bang–bang phase lock loop simulation tool', Design Automation Conference, ASP-DAC'07, Jan 2007, Asia and South Pacific, p. 74–79.
    7. 7)
      • Ramezani, M., Salama, C.A.T.: `Analysis of a half-rate bang–bang phase-locked-loop', Circuits and Systems II: Analog and Digital Processing, IEEE Transactions on, 2002, 49, p. 505–509.
    8. 8)
      • R.C. Walker , B. Razavi . (2003) Designing bang–bang PLLs for clock and data recovery in serial data, Phase-locking in high performance systems – from devices to architectures.
    9. 9)
      • B. Razavi . Challenges in the design high-speed clock and data recovery circuits. IEEE Commun. Mag. , 8 , 94 - 101
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