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Ultra-low power full adder circuit using SOI double-gate MOSFET devices

Ultra-low power full adder circuit using SOI double-gate MOSFET devices

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© The Institution of Engineering and Technology
Published

Proposed is a new, efficient design of a hybrid full adder cell combining two logic styles and a negative differential resistance device realised in a fully depleted silicon on insulator double-gate MOSFET technology. Simulation results show significant (70%) power savings for asymmetric gate work-function and independent gate control full adders with respect to standard CMOS circuits, with lower device count and comparable delay figures.

Inspec keywords: silicon-on-insulator; MOSFET; delays; adders; work function

Other keywords: logic styles; SOI double-gate MOSFET; delay figures; asymmetric gate work-function; negative differential resistance device; ultralow power full adder circuit; independent gate control full adders; device count; hybrid full adder cell; power savings

Subjects: Insulated gate field effect transistors; Logic and switching circuits; Logic circuits

References

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