Your browser does not support JavaScript!
http://iet.metastore.ingenta.com
1887

Area-efficient and self-biased capacitor multiplier for on-chip loop filter

Area-efficient and self-biased capacitor multiplier for on-chip loop filter

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A self-biased capacitor multiplier is proposed to reduce the area of a large integrating capacitor in loop filters. A prototype Σ−Δ fractional-N frequency synthesiser including the capacitor multiplier is fabricated with a 0.35 µm BiCMOS process. The designed capacitor multiplier makes capacitance of 2.72 nF from an on-chip capacitor of 170 pF with current consumption of 240 µA at 2.8 V. The frequency synthesiser demonstrates the in-band phase noise of −79 dBc/Hz at 5 kHz offset.

References

    1. 1)
    2. 2)
      • Hwang, I.-C.: `A Σ−Δ fractional-N synthesizer with a fully-integrated loop filter for a GSM/GPRS direct-conversion transceiver', Dig. Tech. Pprs of IEEE Symp. on VLSI Circuits, 2004, p. 42–45.
    3. 3)
    4. 4)
    5. 5)
http://iet.metastore.ingenta.com/content/journals/10.1049/el_20062486
Loading

Related content

content/journals/10.1049/el_20062486
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address