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Variability-insensitive scheme for NAND flash memory interfaces

Variability-insensitive scheme for NAND flash memory interfaces

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A novel NAND flash memory interface (NFMI) scheme to cope with uncertainty due to process, voltage and temperature (PVT) variations is proposed. The new NFMI scheme introduces a signal called data valid strobe to replace the signal read enable bar, which is a read strobe in the standard NFMI protocol. Experimental results show that the proposed scheme is insensitive to PVT variations, unlike the existing NFMI scheme, and hence substantially increases system performance as well as reliability.

References

    1. 1)
      • Huang, W.-T., Chen, C.-T., Chen, Y.-S., Chen, C.-H.: `A compression layer for NAND type flash memory systems', 3rdInt. Conf. on Information Technology and Applications (ICITA), July 2005, 1, p. 599–604.
    2. 2)
      • Kim, S.-Y., Jung, S.-I.: `A log-based flash translation layer for large NAND flash memory', 8thInt. Conf. on Advanced Communication Technology, 2006. ICACT, February 2006, 3, p. 1641–1644.
    3. 3)
      • Kim, H., Won, Y.: `MNFS: mobile multimedia file system for NAND flash based storage device', 3rdIEEE Consumer Communications and Networking Conf. (CCNC), January 2006, 1, p. 208–212.
    4. 4)
      • Hwang, C.G.: `Where does memory go in the 21C?', Symp. on VLSI Circuits Dig. Tech. Pprs, 2000, p. 88–91.
    5. 5)
      • Samsung Electronics Company: ‘K9F1G08U0A 128M×8-bit NAND flash memory data sheet V1.0’, January 2006.
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