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Robust analogue background calibration technique for multi-bit switched capacitor DACs

Robust analogue background calibration technique for multi-bit switched capacitor DACs

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© The Institution of Engineering and Technology
Published

A robust analogue calibration technique to continuously correct for element mismatch in multi-bit switched capacitor DACs is proposed. Unlike most existing analogue calibration techniques, its accuracy is not limited by the mismatch of charge injection that is outside of the calibration loop. Using the proposed technique, multi-bit switched-capacitor DACs the linearity of which is only limited by the calibration loop gain can be realised. Simulation results show that the INL of a switched-capacitor DAC improves from 8-bit level to 15-bit level with the proposed calibration.

Inspec keywords: digital-analogue conversion; switched capacitor networks; calibration

Other keywords: analogue calibration; digital-analogue converter; multibit switched capacitor DAC; charge injection mismatch; element mismatch

Subjects: Time varying and switched networks; A/D and D/A convertors

References

    1. 1)
    2. 2)
      • Bosi, A., Panigada, A., Cesura, G., Castello, R.: `An 80 MHz 4x times oversampled cascaded delta sigma pipelined ADC with 75 dB DR and 87 dB SFDR', IEEE Int. Solid-State Circuits Conf., February 2005, p. 174.
    3. 3)
    4. 4)
      • C.C. Enz , G.C. Temes . Circuit techniques for reducing the effect of op-amp imperfections: auto-zeroing, correlated double sampling, chopper stabilization. Proc. IEEE , 1584 - 1614.
    5. 5)
      • Yang, Y., Chokhawala, A., Alexander, M., Melanson, J., Hester, D.: `A 114 dB 68 mW chopper-stabilized stereo multi-bit audio A/D converter', IEEE Int. Solid-State Circuits Conf., February 2003, XLVI, p. 56–57.
    6. 6)
    7. 7)
      • Huang, Q., Francese, P.A., Martelli, C., Nielsen, J.: `A 200MS/s 14b 97 mW DAC in 0.18 µm CMOS', IEEE Int. Solid-State Circuits Conf., February 2004, XVII, p. 364–365.
    8. 8)
      • Moon, U., Silva, J., Steensgaard, J., Temes, G.C.: `A switched-capacitor DAC with analog mismatch correction', Proc. ISCAS, May 2000, 4, p. 421–424.
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