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Low-voltage power-efficient adaptive biasing for CMOS amplifiers and buffers

Low-voltage power-efficient adaptive biasing for CMOS amplifiers and buffers

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Novel adaptive biasing techniques, suited for low-voltage operation, are presented. They provide small and accurately controlled quiescent currents, which are automatically boosted when an input signal is applied. Measurement results of an OTA using these techniques and fabricated in a 0.5 µm CMOS technology show a slew rate of more than 40 V/µs for an 80 pF load capacitance and a static power consumption of only 140 µW.

Inspec keywords: CMOS analogue integrated circuits; operational amplifiers; buffer circuits; capacitance

Other keywords: CMOS buffers; OTA; static power consumption; 80 pF; CMOS amplifiers; CMOS technology; slew rate; capacitance; low-voltage operation; operational transconductance amplifier; 0.5 micron; low-voltage power-efficient adaptive biasing; quiescent current; 140 muW

Subjects: Semiconductor integrated circuit design, layout, modelling and testing; Amplifiers; Analogue circuit design, modelling and testing

References

    1. 1)
      • M.G. Degrauwe . Adaptive biasing CMOS amplifiers. IEEE J. Solid State Circuits , 310 - 316
    2. 2)
      • Ramírez-Angulo, J.: `The flipped voltage follower: a useful cell for low-voltage low-power circuit design', Proc. ISCAS 2002, Scottsdale, AZ, USA, p. 615–618.
    3. 3)
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