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Low power clock generator based on area-reduced interleaved synchronous mirror delay

Low power clock generator based on area-reduced interleaved synchronous mirror delay

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Published

A new interleaved synchronous mirror delay (SMD) is proposed to reduce circuit size. In addition, the proposed interleaved SMD solves the polarity problem with just one extra inverter. Simulation results show that about 30% power reduction and 40% area reduction are achieved in the proposed interleaved SMD.

Inspec keywords: low-power electronics; delay circuits; integrated circuit design; VLSI; delays; clocks; synchronisation; SPICE; circuit simulation; logic gates

Other keywords: area reduction; interleaved synchronous mirror delay; power reduction; circuit size reduction; simulation; area-reduced interleaved synchronous mirror delay; VLSI systems; polarity problem; HSPICE simulation; inverter; clock synchronisation; low power clock generator; interleaved SMD

Subjects: Logic circuits; Other digital circuits; Digital circuit design, modelling and testing; Semiconductor integrated circuit design, layout, modelling and testing

References

    1. 1)
      • T. Saeki , Y. Nakaoka , M. Fujita , A. Tanaka , K. Nagata , K. Sakakibara , T. Matano , Y. Hoshino , K. Miyano , S. Isa , S. Nakazawa , E. Kakehashi , J. Drynan , M. Komuro , T. Fukase , H. Iwasaki , M. Takenaka , J. Sekine , M. Igeta , N. Nakanishi , T. Itani , H. Yoshida , K. Yoshino , S. Hashimoto , T. Yoshii , M. Ichinose , T. Imura , M. Uziie , S. Kikuchi , K. Koyama , Y. Fukuzo , T. Okuda . A 2.5-ns clock access, 250-MHz, 256-Mb SDRAM with synchronous mirror delay. IEEE J. Solid-State Circuits , 11 , 1656 - 1668
    2. 2)
      • D. Shim , D. Lee , S. Jung , C. Kim , W. Kim . An analog synchronous mirror delay for high-speed DRAM application. IEEE J. Solid-State Circuits , 4 , 484 - 493
    3. 3)
      • Saeki, T., Nakamura, H., Shimizu, J.: `A 10 ps jitter 2 clock cycle lock time CMOS digital clock generator based on an interleaved synchronous mirror delay scheme', Proc. Symp. VLSI Circuits, 1997, Kyoto, Japan, p. 109–110.
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