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1887

Low power flip-flop with clock gating on master and slave latches

Low power flip-flop with clock gating on master and slave latches

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Published

A new flip-flop is presented in which power dissipation is reduced by deactivating the clock signal on both the master and slave latches when there are no data transitions. The new circuit overcomes the clock duty-cycle constraints of previously proposed gated flip-flops. The power consumption of the presented circuit is significantly lower than that of a conventional flip-flop when the D input has a reduced switching activity.

Inspec keywords: low-power electronics; integrated logic circuits; flip-flops; timing

Other keywords: power dissipation reduction; master latches; clock signal deactivating; slave latches; D input; clock gating; clock duty-cycle constraints; low power flip-flop; reduced switching activity

Subjects: Logic and switching circuits; Logic circuits

References

    1. 1)
      • A.P. Chandrakasan , S. Sheng , R.W. Broderson . Low-power CMOS digital design. IEEE J. Solid-State Circuits , 4 , 473 - 484
    2. 2)
      • T. Lang , F. Musoll , J. Cortadella . Individual flip-flops with gated clocks for low power datapaths. IEEE Trans. Circuits Syst. II , 6 , 507 - 516
    3. 3)
      • M. Nogawa , Y. Ohtomo . A data-transition look-ahead DFF circuit for statistical reduction inpower consumption. IEEE J. Solid-State Circuits , 5 , 702 - 706
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