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Coprocessor for accelerated bit-true simulation of DSP applications

Coprocessor for accelerated bit-true simulation of DSP applications

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Bit-true simulation in DSP applications is very time consuming in comparison to functional-true simulation. This is caused by discrepancies in the finite word length features between the application and the simulating processor. The authors present a method for accelerating bit-true simulation based on a coprocessor with dedicated instructions.

Inspec keywords: digital signal processing chips; digital simulation; signal processing; coprocessors

Other keywords: DSP applications; accelerated bit-true simulation; coprocessor; dedicated instructions

Subjects: Signal processing and detection; Microprocessors and microcomputers; Simulation techniques; Digital signal processing; Digital signal processing chips

References

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      • De Coster, L., Adé, M., Lauwereins, R., Peperstraete, J.A. : `Code generation for compiled bit-true simulation of DSPapplications', Proc. Int. Symp. on System Synthesis, 1998, p. 9–14.
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      • Loughborough Sound Images, `DSP56000 PC System Board User's Manual', 1993.
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      • Hauser, J.R., Wawrynek, J.: `Garp: A MIPS processor with a eeconfigurable coprocessor', Proc. IEEE Symp. Field-Programmable Custom Computing Machines, 1997.
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      • Mentor Graphics, `DSP Station DSP56000 Code Generation User's Manual', 1996.
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      • Kim, S., Sung, W.: `Fixed-point simulation utility for C and C++ based digitalsignal processing programs', Proc. Asilomar Conf., 1994, 1, p. 162–166.
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      • Wirthlin, M.J., Hutchings, B.L.: `A dynamic instruction set computer', Proc. IEEE Workshop on FPGAs for CustomComputing Machines, 1995, p. 99–107.
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