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Scalar quantisation using a fast systolic array

Scalar quantisation using a fast systolic array

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  • Author(s): G.M. Megson 1  and  E. Diemoz 2
    • View affiliations
    • Affiliations: 1: Department of Computer Science, Parallel Emergent and Distributed Architectures Laboratory, University of Reading, Reading, United Kingdom
      2: School of Computing & Mathematics, University of Teeside, Middlesborough, United Kingdom
  • Source: Volume 33, Issue 17, 14 August 1997, p. 1435 – 1437
    DOI:  10.1049/el:19970993 , Print ISSN 0013-5194, Online ISSN 1350-911X
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A systolic array capable of outperforming a table look-up quantiser is proposed. The design has high throughput, can perform uniform or non-uniform quantisation and is suitable for VLSI or field programmable gate array (FPGA) implementation. In the latter case, the array can be used dynamically to both reduce latency and switch between quantisers without the need to reset look-up tables.

Inspec keywords: VLSI; field programmable gate arrays; data compression; quantisation (signal); systolic arrays

Other keywords: high throughput; nonuniform quantisation; field programmable gate array; fast systolic array; FPGA implementation; scalar quantisation; VLSI implementation; uniform quantisation

Subjects: Logic and switching circuits; Signal processing and detection; Semiconductor integrated circuits; Digital signal processing; Logic circuits

References

    1. 1)
      • M. Kavoc , N. Ranganathan . JAGUAR: A fully pipelined VLSI architecture for JPEGimage compression standard. Proc. IEEE , 2 , 247 - 258
    2. 2)
      • A. Mukherjee , N. Ranganathan , M. Bassiouni . Efficient VLSI designs for data transformationof tree-based codes. IEEE Trans. Circuits Syst. , 306 - 314
    3. 3)
      • K. Sayood . (2000) Introduction to data compression.
    4. 4)
      • J.L. Hennessy , D.A. Patterson . (1996) Computer architecture a quantitive approach.
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