BiCMOS circuit optimisation technique linking channel width of MOS device to collector design of BJT

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BiCMOS circuit optimisation technique linking channel width of MOS device to collector design of BJT

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A methodology to optimise the propagation delay of BiCMOS/BiNMOS circuits for high level injection is proposed. It is based on modifying the collector design of the BJT in association with an increase in the channel width of the MOS device to account for the speed degradation caused by the onset of high level injection. A sensitivity-type approach has been adopted to link the value of the channel width of the MOS device to the collector profile of the BJT.

Inspec keywords: BiCMOS integrated circuits; integrated circuit design; circuit optimisation

Other keywords: propagation delay; BJT; sensitivity; BiCMOS circuit optimisation; speed; MOS device; channel width; high level injection; collector design; BiNMOS circuit

Subjects: Mixed technology integrated circuits; Optimisation techniques

References

    1. 1)
      • A. Bellaouar , S.H.K. Embabi , M.I. Elmasry . Scaling of digital BICMOS circuits. IEEE J. Solid-State Circuits , 4 , 932 - 941
    2. 2)
      • P.A. Raje , K.C. Saraswat , K.M. Cham . Accurate delay models for digital BICMOS. IEEE Trans. Electron Dev. , 6 , 1456 - 1464
    3. 3)
      • R.F. Krick , L.T. Clark , D.J. Deleganes , K.L. Wong , R. Fernando , G. Debnath , J. Banik . A 150MHz 0.6 µm BiCMOS superscalar microprocessor. IEEE J. Solid-State Circuits , 12 , 1455 - 1462
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19961544
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