Precise delay generation using the Vernier technique

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Precise delay generation using the Vernier technique

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The authors show a new technique for generating precise clock delays. The Vernier technique exploits the difference between two coarse delays to achieve delay resolutions much smaller than an intrinsic gate delay. This resolution limit is usually smaller than a conventional gate delay, the limit for most conventional delay generation methods. The Vernier technique has the additional advantage of being easy to implement. Simulations show that this technique is capable of resolutions as small as 50 ps using 2.0 µm CMOS.

Inspec keywords: synchronisation; CMOS digital integrated circuits; delay circuits; timing

Other keywords: resolution limit; clock delays; CMOS; Vernier technique; precise delay generation

Subjects: CMOS integrated circuits; Other digital circuits

References

    1. 1)
      • J. Maneatis , M.A. Horowitz . Precise delay generation using coupled oscillators. IEEE J. Solid-State Circuits , 12 , 1273 - 1282
    2. 2)
      • N. Yamanaka , S. Kikuchi . Gbit/s programmable delay-line IC for high-speed pipelining data transmission. Trans. IEICE , 6 , 695 - 697
    3. 3)
      • B. Kim , D. Helman , P.R. Gray . A 30-MHz hybrid analog/digital clock recovery circuit in 2-/mµmCMOS. IEEE J. Solid-State Circuits , 6 , 1385 - 1394
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