Planarised interconnection technology using a new pillar formation method with multi-stacked metal structure

Access Full Text

Planarised interconnection technology using a new pillar formation method with multi-stacked metal structure

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Add to cart
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)
Add to cart

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend Title Publication to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

© IEE
Published

A multilevel interconnection technology using both a new pillar structure consisting of multi-stacked metal layers and chemical-mechanical polishing planarisation has been proposed. This has several advantages such as self-aligned interconnection and decreased via-pillar resistance. The via-pillar resistance becomes one third of conventional via. In addition this method can improve the planarisation capability of inter-metal dielectrics.

Inspec keywords: electric resistance; integrated circuit metallisation; ULSI; polishing; integrated circuit interconnections

Other keywords: pillar formation method; via-pillar resistance; planarised interconnection technology; ULSI; multilevel interconnection technology; multistacked metal structure; planarisation capability; inter-metal dielectrics; self-aligned interconnection; chemical-mechanical polishing

Subjects: Metallisation and interconnection technology; Surface treatment (semiconductor technology); Semiconductor integrated circuits

References

    1. 1)
      • T. Ohba . Chemical-vapour-deposited tungsten for vertical wiring. MRS Bulletin , 11 , 46 - 52
    2. 2)
      • Park, I.S., Park, C.S., Choi, G.H., Wee, Y.J., Kim, I.C., Koh, K.M., Lee, H.-D., Lee, S.I., Lee, M.Y.: `Fabrication of 256 Mbit DRAM with a fully planarised double level interconnection', Proc. of IEEE VMIC Conf., 1995, Santa Clara, p. 45.
    3. 3)
      • Park, M., Kim, G.H., Park, J.M., Kim, S.G., Hyeon, Y.C., Koo, J.G., Nam, K.S.: `Multilevel interconnection technology using new pillar formation methodand planarisation', Proc. of IEEE CMP-MIC Conf., 1996, Santa Clara, p. 291.
    4. 4)
      • R.V. Joshi , M. Tejwani . Low temperature, low resistivity sub-half micron via/interconnect structureusing reaction of Al-alloys and germane. IEDM Tech. Dig. , 257 - 260
    5. 5)
      • Ueda, T., Uehara, T., Nishio, M.: `One mask interconnect / via formation technology horizontal mask patternto vertical topography', Proc. of IEEE VMIC Conference, 1995, Santa Clara, p. 38.
    6. 6)
      • K. Ueno , K. Ohto , K. Tsunenari , K. Kajiyana , K. Kikuta , T. Kikkawa . A quartermicron planarised interconnection technology with self-alignedplug. IEDM Tech. Dig. , 305 - 308
    7. 7)
      • Pramanik, D., Jam, V., Gabriel, C., Weling, M., Baker, D., Eakin, J.: `A submicron triple level metallisation process for high performance applicationspecific circuits', Proc. of IEEE VMIC Conf., 1992, Santa Clara, p. 37.
    8. 8)
      • Park, M., Kim, S.G., Park, J.M., Kim, G.H., Koo, J.G., Yoo, H.J., Nam, K.S., Jang, J.: `The characteristics of gap filling and planarisation by using multi-stepsputtering PECVD and CMP process', Proc. of IEEE VMIC Conf., 1995, Santa Clara, p. 271.
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19961143
Loading

Related content

content/journals/10.1049/el_19961143
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading