Crystalline pMOS inverter using amorphous thin film transistor as active load

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Crystalline pMOS inverter using amorphous thin film transistor as active load

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© The Institution of Electrical Engineers
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The integration of the amorphous silicon (a-Si:H) thin film transistor on top of a crystalline p-type silicon metal–oxide–semiconductor (pMOS) transistor to serve as active load has been achieved successfully. The vertical integration of crystalline silicon and amorphous silicon circuits to form the three dimensional structure is a promising technique for future application in high density memory cells and neural network image sensors.

Inspec keywords: integrated circuit technology; MOS integrated circuits; VLSI; thin film transistors; insulated gate field effect transistors; integrated memory circuits; logic gates

Other keywords: crystalline Si transistor; 3D ICs; amorphous Si:H transistor; neural network image sensors; high density memory cells; vertical integration

Subjects: Memory circuits; Other MOS integrated circuits; Thin film circuits; Insulated gate field effect transistors; Logic circuits

References

    1. 1)
      • Uemoto, Y., Fujii, E., Nakamura, A., Senda, K.: `A high-performance stacked-CMOS SRAM cell by solid phase growth technique', Proc. IEEE 1990 Symp., 1990, VLSI Technology, p. 21–22.
    2. 2)
      • Adan, A.O., Suzuki, K., Shibayama, H., Miyake, R.: `A half-micron SRAM cell using a double-gated self-aligned polysilicon PMOS thin film transistor load', Proc. IEEE 1990 Symp., 1990, VLSI Technology, p. 19–20.
    3. 3)
      • Kinugawa, M., Kakuma, M., Yoshida, T., Nakayama, T., Morita, S., Kubota, K., Matsuoka, F., Oyamatsu, H., Ochii, K., MacGuchi, K.: `TFT (thin film transistor) cell technology for 4 Mbit and more high density SRAMs', Proc. IEEE 1990 Symp., 1990, VLSI Technology, p. 23–24.
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