http://iet.metastore.ingenta.com
1887

Four-quadrant multiplier combining sigma-delta and multirate processing techniques

Four-quadrant multiplier combining sigma-delta and multirate processing techniques

For access to this article, please select a purchase option:

Buy article PDF
£12.50
(plus tax if applicable)
Buy Knowledge Pack
10 articles for £75.00
(plus taxes if applicable)

IET members benefit from discounts to all IET publications and free access to E&T Magazine. If you are an IET member, log in to your account and the discounts will automatically be applied.

Learn more about IET membership 

Recommend to library

You must fill out fields marked with: *

Librarian details
Name:*
Email:*
Your details
Name:*
Email:*
Department:*
Why are you recommending this title?
Select reason:
 
 
 
 
 
Electronics Letters — Recommend this title to your library

Thank you

Your recommendation has been sent to your librarian.

A mixed analogue-digital solution combining sigma-delta and multirate processing techniques is proposed for realising four-quadrant multipliers. This overcomes the major limitations of purely analogue circuits and still achieves the attractive benefits of low power consumption and small chip size which cannot be afforded using digital signal processing techniques together with auxiliary analogue-digital and digital-analogue convertors.

References

    1. 1)
      • Integrated MOS four-quadrant analog multiplier using switched capacitor technology for analog signal processor IC's
    2. 2)
      • New four-quadrant CMOS analogue multiplier
    3. 3)
      • Watanabe, K., Temes, G.C.: `A switched-capacitor digital multiplier', Proc. Symp. Circuits and Systems, 1983, p. 1270–1273
    4. 4)
      • The design of sigma-delta modulation analog-to-digital converters
    5. 5)
      • Nonrecursive polyphase switched-capacitor decimators and interpolators
    6. 6)
      • FIR switched-capacitor decimators with active-delayed block polyphase structures
    7. 7)
      • Grilo, J., Franca, J.E.: `Mixed analog-digital correlator using sigma-delta and multirate processing techniques', Proc. of Midwest Symp. Circuits and Systems, May 1991, Monterey, USA
http://iet.metastore.ingenta.com/content/journals/10.1049/el_19911329
Loading

Related content

content/journals/10.1049/el_19911329
pub_keyword,iet_inspecKeyword,pub_concept
6
6
Loading
This is a required field
Please enter a valid email address