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Four-quadrant multiplier combining sigma-delta and multirate processing techniques

Four-quadrant multiplier combining sigma-delta and multirate processing techniques

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© The Institution of Electrical Engineers
Published

A mixed analogue-digital solution combining sigma-delta and multirate processing techniques is proposed for realising four-quadrant multipliers. This overcomes the major limitations of purely analogue circuits and still achieves the attractive benefits of low power consumption and small chip size which cannot be afforded using digital signal processing techniques together with auxiliary analogue-digital and digital-analogue convertors.

Inspec keywords: multiplying circuits; application specific integrated circuits

Other keywords: sigma delta modulation; mixed analogue-digital solution; multirate processing techniques; low power consumption; small chip size; mixed mode ASIC; four-quadrant multipliers

Subjects: Semiconductor integrated circuits; Mixed analogue-digital circuits

References

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      • C.W. Kim , S.B. Park . New four-quadrant CMOS analogue multiplier. Electron. Lett. , 24 , 1268 - 1270
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      • Watanabe, K., Temes, G.C.: `A switched-capacitor digital multiplier', Proc. Symp. Circuits and Systems, 1983, p. 1270–1273.
    5. 5)
      • Grilo, J., Franca, J.E.: `Mixed analog-digital correlator using sigma-delta and multirate processing techniques', Proc. of Midwest Symp. Circuits and Systems, May 1991, Monterey, USA.
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      • J.E. Franca . Nonrecursive polyphase switched-capacitor decimators and interpolators. IEEE Trans. , 9 , 877 - 887
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      • T. Enomoto , M.-A. Yasumoto . Integrated MOS four-quadrant analog multiplier using switched capacitor technology for analog signal processor IC's. IEEE J. Solid-State Circuits , 4 , 852 - 859
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