Secco and periodic etches have been used to delineate n⁺p and p⁺n junctions found in ULSI CMOS. Preliminary trials indicated that delineated depth depends on etch time. An interpretation of these results in terms of etching of the substrate material leads to a simple expression between delineated depth and etch time. Once this relation has been established the technique allows a quick and consistent check on two dimensional dopant profiles and has been used on shallow junctions found in deep submicrometre structures.