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Unidirectional-flow systolic array for linear discriminant function classifier

Unidirectional-flow systolic array for linear discriminant function classifier

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© The Institution of Electrical Engineers
Published

A unidirectional flow systolic array with 100% efficiency is described for the linear discriminant classifier. To obtain this solution, a two-stage transformation technique is applied to previous reported contraflow array. In the first stage, unidirectional data flow is incorporated. In the second stage, data retiming is performed combined with modifications in the clocking scheme.

Inspec keywords: logic arrays; computerised pattern recognition; computerised signal processing; cellular arrays; digital signal processing chips

Other keywords: clocking scheme modifications; unidirectional data flow; contraflow array; two-stage transformation technique; linear discriminant classifier; unidirectional flow systolic array; data retiming

Subjects: Microprocessor chips; Logic circuits; Digital signal processing; Microprocessors and microcomputers; Pattern recognition

References

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      • Liu, H.H., Fu, K.S.: `A VLSI systolic processor for fast seismic classification', Proc. 1983 Int. Symp. VLSI Tech., Sys. and Appl., 1983, Taipei, Taiwan, p. 240–243.
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      • Urquhart, R.B.: `VLSI architectures for the linear discriminant function classifier', IEEE Proc. Computer Architectures for Pattern Analysis and Image Database Management, October 1983, p. 223–232.
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