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New CMOS resistor implementation for linear IC applications

New CMOS resistor implementation for linear IC applications

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A new CMOS implementation for a linearised floating resistance is presented, where the resistor value depends only on the β of a matched set of nMOS transistors, and on a bias current IB; it is independent of the threshold voltage VT. Simulated worst-case linearity for a unity-gain amplifier is around 1% for a ±2 V output swing.

References

    1. 1)
      • M. Banu , Y. Tsividis . Floating voltage-controlled resistors in CMOS technology. Electron. Lett. , 678 - 679
    2. 2)
      • Masuda, S., Kitamura, Y.: `Design considerations of monolithic continuous-time filters', Proc. ISCAS, May 1986, p. 1165–1168.
    3. 3)
      • Y.P. Tsividis , M. Banu , J.F. Khoury . Continuous-time MOSFET-C filters in VLSI. IEEE J. Solid-State Circuits , 15 - 30
    4. 4)
      • Z. Czarnul . Novel MOS resistive circuit for synthesis of fully integrated continuous-time filters. IEEE Trans. , 718 - 721
    5. 5)
      • K.S. Tan , P.R. Gray . Fully integrated analog filters using bipolar-JFET technology. IEEE J. Solid-State Circuits , 814 - 821
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